Special Report
CPU Performance Bottlenecks Limit Parallel Processing Speedups
Hardware optimizations and well-thought-out software architectures can help, but only incrementally.
Top Stories
Analog Consolidation Spurs New Round Of Startups
Smaller companies open the door once again to analog customization projects, which have been too expensive for most chipmakers.
Power Delivery Challenged By Data Center Architectures
More powerful servers are required to crunch more data, but getting power to those servers is becoming complicated.
Voltage Drop Now Requires Dynamic Analysis
Once a manageable effect, voltage drop is causing more problems at lower nodes.
Where Power Savings Really Count
How chiplets and advanced packaging will affect power efficiency, and where design teams can have the biggest impact on energy consumption.
Reusable Power Models
Justifying the creation of a model can be difficult when it is only used for a single task — unless it can be explicitly valued.
Videos
Real-World Applications Of Computational Fluid Dynamics
How faster processing is revolutionizing different industries.
Making Electronics More Efficient
Challenges and future directions for disaggregating SoCs.
Next-Gen High-Speed Communication In Data Centers
New approaches to moving more data faster and more efficiently.
Blogs
Arm’s Sriharsha Vinjamury finds 2nm technology offers significant performance improvements, but costs are higher and detecting defects becomes harder, in Challenges And Outlook Of ATE Testing For 2nm SoCs.
Fraunhofer IIS/EAS’ Björn Zeugmann and Benjamin Prautsch look at strategies to tackle the long development times and high costs of designing and verifying analog components, in Managing Complexity And A Left Shift: Reconfigurable Mixed-Signal Circuits For Complex Integrated Systems.
Synopsys’ Faisal Goriawalla provides an overview of the multi-die test challenges that go beyond the design phase, covering manufacturing and deployment in the field, in Ensuring Multi-Die Package Quality And Reliability.
Rambus’ Tim Messegee digs into the higher bandwidth needed in AI PCs and how DDR5 main memory will push to data rates of 6,400 megatransfers per second (MT/s) and beyond, in Memory Implications Of Gen AI In Gaming.
Cadence’s Frank Ferro shows how AI/ML training models are stressing existing infrastructure and driving the need for memory subsystems that support high data rates, in HBM3E: All About Bandwidth.
Ansys’ Caty Fairclough details how simulation is helping a vertical aircraft developer create a more sustainable future, in Powering The Future Of Flight: Designing A Hydrogen-Powered eVTOL.
Siemens EDA’s Russell Klein points out why HLS is critical for determining which type of processors to use, in Fantastical Creatures.
Sponsor White Papers
A Software-First Mindset For Driving Efficiency And Sustainability For Industrial IoT
Details of the software-defined industrial system and how it reduced latency, enhanced cyber security, eased deployment and maintenance, and accelerated time-to-market.
Joint Interdisciplinary Work To Enable Novel, Industry-Ready Chiplet Solutions
Fraunhofer IIS/EAS’ Chiplet Center of Excellence (CCoE).
Decoding Glitch Power at the RTL Stage
A shift-left approach for glitch power estimation and optimization.
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