Special Report
What’s The Best Way To Sell An Inference Engine?
The hardware choices for AI inference engines are chips, chiplets, and IP. Multiple considerations must be weighed.
Top Stories
Power Budgets Optimized By Managing Glitch Power
While not a focus until now, earlier readings can be made in design to better understand the impact of glitch power.
2025: So Many Possibilities
This will be an incredible year for innovation, driven by AI and for AI, and pushing the limits of fundamental physics.
AI Won’t Replace Subject Matter Experts
But it could help with mundane tasks, freeing up designers to focus on more intricate problems.
Sponsor Blogs
Fraunhofer’s Andy Heinig explains how to reduce risk by distributing the security-critical functionality of a system across different circuits, in Advanced Packaging: A Curse Or A Blessing For Trustworthiness?
Synopsys’ Ron Lowman and Jon Ames show how to tackle the challenges of high-bandwidth, low-latency connectivity and efficient resource management, in How Ultra Ethernet And UALink Enable High-Performance, Scalable AI Networks.
Rambus’ Tim Messegee explores how different flavors of DRAM, including HBM, LPDDR, and GDDR, each fill a particular AI niche, in Choosing The Right Memory Solution For AI Accelerators.
Quadric’s Steve Roddy argues that a partitioned, fallback-style architecture can’t work for modern networks because modern CNNs and new transformers are comprised of much more varied ML network operators, in MACs Are Not Enough: Why “Offload” Fails.
Arm’s Ola Liljedahl looks at best practices for improving throughput and fair access to shared resources, in The When, Why, And How Of Waiting And Backoff In Multi-Threaded Applications On Arm.
Cadence’s Veena Parthan dives into thermal solutions for increasing power density and energy costs, such as direct-to-chip cooling and whole-system immersion cooling, in Is Liquid Cooling The Future Of Your Data Center?
Siemens’ Jeff Wilson outlines ways to meet IR drop mitigation requirements, including power grid enhancement and via insertion, while maintaining design rule compliance and preserving PPA targets, in Tame IR Drop Like Google.
Sponsor White Papers
Achieving Successful Timing, Power, And Physical Signoff For Multi-Die Designs
Traditional 2D EDA flows are insufficient for multi-die designs, requiring advanced parasitic extraction, power analysis, and physical checks.
How Engineering Simulation Drives Impact for Sustainability
New methodology for early-stage and life cycle design that quantifies the impact of simulation on sustainability initiatives.
How Google And Intel Use Calibre DesignEnhancer To Reduce IR Drop And Improve Reliability
How to improve power integrity and achieve DRC-clean layouts with optimal electrical performance.
Why Your Data Center Needs a Digital Twin
Reducing energy costs without risking uptime.
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