Top Stories

Holistic Power Reduction
Minimizing power, energy, or thermal impacts requires a concerted approach throughout the entire design, development, and implementation flow.

Making Tradeoffs With AI/ML/DL
Optimizing tools and chips are opening up new possibilities and adding much more complexity.

Rethinking Engineering Education In The U.S.
Academia, industry partnerships ramp to entice undergrads into hardware engineering.

Blogs

Synopsys’ Manuel Mota looks at ensuring the reliability of multi-die systems with UCIe test and repair, in From Known Good Die To Known Good System With UCIe IP.

Fraunhofer IIS EAS’ Björn Zeugmann and Olaf Enge-Rosenblatt explain why custom circuit design is so important for smart manufacturing, in Circuit Design For Industry 4.0.

Arm’s Mark Knight digs into why mitigating certain threats requires a fundamental change to the familiar model of computer security that relies on a hierarchy of privilege levels, in Making It Easier To Build Platforms That Support Confidential Computing.

Ansys’ Akanksha Soni shows how heat transfer, electromigration, stress and strain, and thermal expansion pose challenges for stacked dies, in 3D-IC Design: An Innovative Approach To Chip Integration.

Cadence’s Veena Parthan points to a geometric concept that helps shorten the time to create an accurate mesh, in High-Fidelity CFD Mesh Generation With Voronoi Diagram.

Siemens EDA’s Janet Attar looks at bringing real route information and parasitics to any step in the place-and-route flow, in Conquer Placement And Clock Tree Challenges In HPC Designs.

Rambus’ Frank Ferro explains why memory throughput speed and low latency are critical as inference shifts from the data center to the network edge, in GDDR6 Delivers The Performance For AI/ML Inference.

Sponsor White Papers

Achieving Consistent RTL Power Accuracy
How to make better decisions about power earlier in the design process.

Placement And CTS Techniques For High-Performance Computing Designs
Tradeoffs and techniques for creating very fast chips.

Engineering Simulation Workloads And The Rise Of The Cloud
How the rise of the cloud for EDA and CAE applications is changing how engineers work.

Achieving Your Low Power Goals With Synopsys Ultra Low Leakage IO
Why are ULL GPIOs needed — what are the optimization techniques used to reduce leakage and the inherent tradeoffs to consider.

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