Top Stories
DRAM Choices Becoming Central Design Considerations
Memory footprint, speed and density scaling are compounded by low-power constraints.
The Challenge Of Optimizing Chip Architectures For Workloads
Hardware/software co-design has progressed beyond mapping one onto the other. It is about holistically solving a problem in the most efficient manner with a given set of constraints.
Improving PPA With AI
New design tools and approaches are surfacing; some are promising.
Standardizing Chiplet Interconnects
Why UCIe is so important for heterogeneous integration.
Blogs
Fraunhofer’s Andy Heinig finds that even large and complex chiplet structures can be designed reliably and efficiently, in Chiplets: Current Status.
Arm’s Lucas Bressan looks at what’s needed for safe, more power-efficient robots, in New Robots Require New Ways To Think About Processors.
Rambus’ Tim Messegee observes that bringing signaling to 64 GT/s required some of the most fundamental changes yet to the PCIe standard, in A Sea Change In Signaling With PCIe 6.0.
Siemens EDA’s Himani Kaushik digs into the shortcomings of traditional block storage and points to two SSD namespace alternatives, in What’s In A Name(Space)? Optimizing SSD Controller Performance And Verification.
Synopsys’ Madhumita Sanyal weighs in on space limitations, co-packed optics, and signal integrity in Ethernet switches for hyperscale data centers, in Meeting 112 SerDes Based System Design Challenges.
Cadence’s Paul McLellan summarizes the latest efforts to build a common, interoperable infrastructure for radio access networks, in Open RAN Phase 2.
White Papers
NVMe-OF: Simple, Invisible Fabric For Distributed Storage Networks.
Every Walk’s A Hit: Making Page Walks Single-Access Cache Hits.
Building High Voltage Automotive Battery Management Systems.
State-Space Model Of An Electro-Mechanical-Acoustic Contactless Energy Transfer System Based On Multiphysics Networks.
How To Create A Physics-Based Laser Compact Model For A Photonic Process Design Kit (PDK).
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