Top Stories

A New Dimension Of Complexity For IC Design
Static timing analysis becomes more difficult in 3D.

Greener Design Verification
Why designing chips is so energy-inefficient, and how that impacts development cost and time to market.

Growth Spurred By Negatives
Sometimes what looks like a negative turns out to be a huge positive, and that is certainly driving the semiconductor and EDA industries into 2022.

Blogs

Technology Editor Brian Bailey contends that verification can be done better and faster, using less energy, if we throw out today’s unethical coverage metrics, in Ethical Coverage.

Cadence’s Frank Schirrmeister looks at big trends from the last decade that are still in full swing, in Three Technologies Enabling The Next Decade Of Hyperconnectivity.

Synopsys’ Hari Sathianathan explains how to formally verify embedded memory designs and their redundancy repair schemes, in Using Symbolic Simulation For SRAM Redundancy Repair Verification.

Siemens’ Pirzad Motafram investigates why coverage and assertion tools are vital to ensuring ICs are production-ready, in Dependable Verification Is The Foundation ICs Require.