Top Stories
Will AI Disrupt EDA?
It’s been decades since there was a disruption within EDA, but AI could change the semiconductor development flow and force changes in chip design.
Floor-Planning Evolves Into The Chiplet Era
Automatically mitigating thermal issues becomes a top priority in heterogeneous designs.
What’s Next In System-Level Design?
As chip complexity rises with disaggregation and chiplets, the design process will become increasingly more workflow- and workload-specific.
Videos
Changes In Formal Verification
Errors in chiplets, automotive safety, processors become key targets.
Blogs
Technology Editor Brian Bailey explains how companies are harvesting expertise from their senior engineers and making it available to new hires and junior engineers, in Capturing Knowledge Within LLMs.
Movellus’ Aakash Jani and Lee Vick show why SDC challenges require a multi-faceted approach involving advanced silicon lifecycle analytics and on-die telemetry, in Droop And Silent Data Corruption.
Siemens EDA’s Michael Walsh, Jin Hou, and Todd Burkholder introduce a new way to functionally verify packaging connectivity using formal verification, in Here At Last! Automated Verification Of Heterogeneous 2D/3D Package Connectivity.
Synopsys’ Eldon Nelson digs into IDEs and how they help address a range of coding challenges, particularly with HDLs like SystemVerilog and VHDL, in Enhancing RTL Design Efficiency: The Power And Benefits Of Integrated Development Environments.
Axiomise’s Ashish Darbari, Fabiana Muto, and Nicky Khodadad report on the good, bad, and unknowns of AI, and what’s missing for design and verification, in Insights From The AI Hardware & Edge AI Summit.
Keysight’s Roberto Piacentini Filho delves into IP catalogs and how they can break down silos by offering centralized repositories and fostering easy collaboration, in Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools.
Cadence’s Rich Chang outlines common debugging issues with solutions to streamline the process and create efficient testbenches for hardware verification, in Debugging SystemVerilog Constraint Randomization: A Comprehensive Guide.
Arteris’ Ashley Stevens discusses the benefits of partitioning the system into shared and non-shared data regions with the shared data routing through a coherent interconnect, in Optimizing Interconnect Topologies For Automotive ADAS Applications.
Sponsor White Papers
Unifying Storage Diversity: Leveraging PCIe IP For Multi-Device, Multi Form Factor Designs
The integration of PCIe interfaces within the context of varying storage device form factors.
Essential Insights For Design PCIe 6.0 Interconnects
Automate the setup and simulation for PAM4 PCIe systems using a smart design environment.
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