Top Stories
Verification Of Functional Safety
Part 1 of 2: How do you trade off cost and safety within an automobile? Plus, a look at some of the challenges the chip industry is facing.
7/5nm Timing Closure Intensifies
The issues may be familiar, but they’re more difficult to solve and can affect everything from performance to yield.
Predictions: Methodologies And Tools
Cloud-based verification and software development, bigger IP blocks, machine learning, and security issues top the list for 2018.
Blogs
Editor In Chief Ed Sperling contends that the creation of new markets for semiconductors could help iron out demand fluctuations, in Hedging The Chip Industry.
Technology Editor Brian Bailey points to what’s changing at DVCon this year and who should attend, in DVCon Committee Picks.
Mentor’s Mark Olen finds that SoC development has hit a bottleneck when it comes to re-using verification stimulus, in Raising SoC Development Productivity With Portable Stimulus.
OneSpin’s Sergio Marchese explains why more engineers want to become experts in formal verification, in Formal In The Spotlight.
Synopsys’ Ruben Molina observes that new transistor architectures also mean new parasitic effects to watch out for, in 3D Extraction Necessities For 5nm And Below.
Cadence’s Frank Schirrmeister details why sharing expertise is necessary for a robust SoC ecosystem, in It Takes A Village…To Develop And Verify SoCs.
Aldec’s Sunil Sahoo compares waveform analysis to data plots, in Analyzing Data Differently.
eSilicon’s Mike Gianfagna zeroes in on what’s ahead for advanced ASICs, with In Case You Missed It.
