Top Stories
The Challenge Of RISC-V Compliance
Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.
The Problem With Post-Silicon Debug
Rising costs, tighter market windows and more heterogeneous designs are forcing chipmakers to rethink fundamental design approaches.
Can Debug Be Tamed?
Can machine learning bring debug back under control?
Video
New Memory Options
Using data as the starting point for designs opens up new architectural choices.
Reverse Debug
How to reduce time spent on debugging complex chips.
Blogs
Editor In Chief Ed Sperling argues that even before the industry begins shifting to a data-driven approach, ground rules need to be established, in Crisis In Data.
Technology Editor Brian Bailey questions whether antitrust law needs updating for the data age, in Follow The Data.
Mentor’s Ahmed Ramadan and Greg Curtis warn that because devices need to operate reliably for longer than ever before, aging simulation is vital, in The Time Is Now For A Common Model Interface.
Synopsys’ Tom De Schutter examines the benefits of starting early on the complex firmware development required by next-generation SSDs, in Accelerate SSD Software Development And System Validation.
Cadence’s Frank Schirrmeister provides 5 takeaways from Embedded World 2019, from safety and security to ecosystems, in Hot Technologies In Cold Weather.
OneSpin’s Sven Beyer explains why as RISC-V offerings expand, it’s vital to make sure they conform to the ISA specification, in Formal Verification Of RISC-V Cores.
Silexica’s Andrew Caples explains that embedded software development is no longer a one-dimensional problem and tools need to adapt, in Inaccurate Assumptions Mean Software Issues.
UltraSoC’s Andy Gothard looks at how RISC-V’s open-source ISA ecosystem is taking big steps forward with the latest foundation member announcements, in The Rapid Rise Of RISC-V.
eSilicon’s Mike Gianfagna describes presenting a paper at ISSCC, in A Conference For The Ages.
