Top Stories

Pain Points At 7nm
More rules, variation and data expected as IP and tools begin early qualification process.

A Formal Transformation
Exclusive: What happens when you put formal leaders from all over the world in the same room and give them an hour to discuss deployment?

Coherency, Cache And Configurability
The fundamentals of improving performance.

Are Simulation’s Days Numbered?
Experts at the table, part 1: The verification of blocks and IP is undergoing significant change and the experts have some diverse opinions on the way forward including the role of simulation.

Blogs

Editor in Chief Ed Sperling contends that the repositioning of the semiconductor industry has finally begun, in It’s Transition Time.

Technology Editor Brian Bailey points to a growing divide between the design team, which is stuck using old technology, and rapidly advancing verification technologies, in An Unsustainable Divide.

Cadence’s Frank Schirrmeister observes that it’s still too early to tell if the changes underway are positive or negative, in How Do Design And Verification Change In The IoT Age?

Aldec’s Jacek Majkowski provides a hardware emulation guide for non-C designers, in Why I See C In SCE-MI.

Mentor Graphics’ Alex Grange and PTC’s Linda Mazzitelli examine the trouble that poor communication can cause, in Enhanced Electro-Mechanical Collaboration.

NetSpeed Systems’ Sundari Mitra argues that engineering schools need to revamp their curricula to address real-world problems, in The Making Of A System Architect.

Synopsys’ Tom De Schutter looks at best practices in FPGA-based prototyping from experts at NVIDIA, Intel, Synopsys, SanDisk and Cisco, in Prototype Like A Pro.

eSilicon’s Mike Gianfagna finds high-school kids building autonomous systems using 3D printers, in Robotics Update From The Playing Field.

OneSpin’s Dave Kelf points to a new, unbiased site for formal verification technology, in Everything You Wanted To Know About Formal, But Were Too Afraid To Ask.

Arteris’ Kurt Shuler digs into what you don’t know about getting SoC projects to market, in Why Is Semiconductor Schedule Predictability Boring?