Top Stories

Speeding Up Neural Networks
Adding more dimensions creates more data, all of which needs to be processed using new architectural approaches.

Design Complexity Drives New Automation
It now takes an entire ecosystem to build a chip—and lots of expensive tools.

Whatever Happened To High-Level Synthesis?
What progress has been made in High Level Synthesis and what can we expect in the near future?

Blogs

Editor In Chief Ed Sperling finds that after decades of failing to live up to expectations, massively parallel systems finally are getting serious attention, in The Rise Of Parallelism.

Technology Editor Brian Bailey argues that it’s our own fault so little research is being conducted in EDA, in Researchers Learn New Tricks.

Mentor’s Mike Santarini questions whether there is a better way to predict growth for individual segments than industry-wide forecasts, in Mathematic Model Helps Predict Markets That Will Drive Semiconductor Growth.

OneSpin’s Dave Kelf contends that it’s time to leverage comprehensive assertion-based verification, in Rediscovering Coverage Insurance.

Synopsys’ Malte Doerper points to the benefits of virtual prototyping for SSD and NAND controller software development, in Wear Down Your Virtual Prototype.

Cadence’s Frank Schirrmeister provides examples of the next productivity leap in verification, in Avoiding A $7.7B Chip Design Cost.

eSilicon’s Mike Gianfagna compares 2.5D design to the first trips in space, in Historic FinFET/2.5D Firsts.

Aldec’s Krzystof Szcur examines software as a way of driving design under test on an FPGA prototyping platform, in Software-Driven Test Of FPGA Prototype.

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