Top Stories

ESL Flow is Dead
Expecting the future to replicate the past always leads to surprises and when it comes to migration of abstraction for semiconductor design, the future remains unclear.

Way Too Much Data
Each new node and architectural change results in an explosion of data, making optimization of designs significantly harder.

Bridging Hardware And Software
The need for concurrent hardware-software design and verification is increasing, but are engineering teams ready?

System-Level Verification Tackles New Role
The role of system-level verification is not the same as block-level verification and requires different ways to think about the problem.

Blogs

Editor In Chief Ed Sperling contends that the frenzy of M&A activity in the semiconductor industry could backfire, in Cheap Money Effects.

eSilicon’s Mike Gianfagna questions who will get a boost from the IoT market, in On The Verge.

Aldec’s Henry Chan digs into creating an anatomically correct model for poking and prodding, in UVM Register Layer: The Structure.

ARM’s Ronan Synnott explains how to build and debug code for a mix of processor cores, in Better Heterogeneous CPU Designs.

Agnisys’ Anupam Bakshi observes that while more registers equate to more functionality and configurability, more isn’t always better, in Making Way For Register Specification Software.

OneSpin Systems’ Dave Kelf contends that formal can’t be left to a specialized few because success depends on the entire project team, in The Early Bird Catches The Bug Using Formal.

Synopsys’ Malte Doerper examines the role of virtual prototypes in risk management, in Earthquake Proof Your Software Development.

Cadence’s Frank Schirrmeister points to emulation highlights from the recent CDNLive conference, in Stories From The Village Called Hardware-Assisted Development.

Mentor Graphics’ Nicolas Williams points to the unique design requirements when sending an ADC into space, in Deep Space Design Considerations.