Top Stories
How To Integrate An Embedded FPGA
Adding an eFPGA into an SoC is more complex than just adding an accelerator.
Why IP Quality Is So Difficult To Determine
How it is characterized, verified and used can have a big impact on reliability and compatibility in a design.
Adding Order And Structure To Verification
How industry experts reacted to their first encounter with a formal capability maturity model.
Video
Analog Fault Simulation
How to improve coverage in safety-critical designs.
Blogs
Editor in Chief Ed Sperling contends that current implementations of AI have just scratched the surface of what this technology can do, which creates its own set of issues, in How Far Can AI Go?
Technology Editor Brian Bailey observes that the slowdown in Moore’s Law is opening the door to more open-source IP and EDA, in Moore Open Source Coming.
Mentor’s Chris Giles points out that digital systems need clocks, but today’s designs require more from clocking schemes than ever before, in FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools.
Synopsys’ Shreedhar Ramachandra and Himanshu Bhatt explain how to use UPF information model APIs to write reusable low-power testbenches that can monitor and control UPF objects, in Shift-Left Low Power Verification With UPF Information Model.
OneSpin’s John Hallman warns that as the supply chain of components and IP expands, so do the opportunities for adversarial tampering, in Intellectual Property: Trust… But Verify.
eSilicon’s Mike Gianfagna reveals a collaboration that overcomes tough signal and power integrity challenges, in Delivering High-Speed Communications: The Back Story.
And in case you missed it, check out the special report, 3D NAND Race Faces Huge Tech And Cost Challenges, to learn more about the looming shakeout as memory vendors struggle to find ways to add more layers and increase density.
