Top Stories

Respecting Reset
Reset is one of the most important signals in a design and yet perhaps one of the least respected. What can go wrong and how to correct it.

Toward Continuous HW-SW Integration
Increased complexity and heterogeneity are prompting new methods that can avert surprises at the end of the design cycle.

Verification Unification
The verification task relies on both dynamic execution and formal methods today, but those technologies have few connection points. That may be changing with Portable Stimulus.

Blogs

Editor in Chief Ed Sperling digs into what multiple process nodes and market uncertainties really mean to the design world, in Foundry Wars, Take Two.

Synopsys’ Tom De Schutter spotlights different goals and approaches that are required, in Verification and Validation Don’t Mean The Same Thing.

OneSpin’s Dave Kelf points to various ways formal verification is deployed across the world, in Formal Verification’s Continental Divide.

Cadence’s Frank Schirrmeister looks into the key components that allow IP development in a cycle-accurate SoC context, in Emulation Enabling Automotive Designs.

Netspeed’s Rajesh Ramanujam questions whether achieving functional safety goals is possible without compromising PPA, in Boldly Go Where No NoC Has Gone Before.

Mentor’s John Parry examines the role of packaging in achieving “as-designed” thermal performance, in Huawei Delivers Outstandingly Accurate Models.

Aldec’s Henry Chan explains why the past few months are just a blur, in It’s Show Time.

ARM’s Stephen Baron provides a peek into what you’ll see next, in Capturing The Future, Frame By Frame.