Top Stories

Hardware-Software Co-Design Reappears
There may be a second chance for co-design, but the same barriers also may get in the way.

Hybrid Emulation Takes Center Stage
Complex chips require a multitude of verification platforms working in sync, and that’s where the challenges begin.

How To Optimize Verification
There’s no such thing as a perfect strategy, but much can be improved.

Blogs

Editor in Chief Ed Sperling contends that China’s backing of homegrown tech stocks is the next phase in a much larger plan, in China Accelerates Its Timetable.

Technology Editor Brian Bailey explores once-great mammoths of the semiconductor industry now on the brink of extinction, in Semiconductor’s Dinosaurs.

Cadence’s Frank Schirrmeister contends that a system-wide view is required for designing new 5G applications, from fixed wireless access to mission-critical devices, in Verification Requirements For 5G To Enable A Perfect Storm Of New Applications.

Synopsys’ Pat Sheridan explains how to analyze problems earlier with static timing analysis-based activity delay shifting and glitch power analysis, in Which Glitch Is Which?

Mentor’s Omar El-Sewefy shows how to get the most out of cloud computing resources by following a few guidelines, in Taking EDA To The Cloud.

eSilicon’s Mike Gianfagna recounts how embedded memory started as a foundational element in chip design and has now arrived as a substantial differentiating element, in Memory IP: From Cobblestone To Cornerstone.

Silexica’s Zubair Wadood digs into the design flow steps used to convert C/C++ algorithms to a hardware implementation, in Optimize MATLAB C/C++ Code For HLS.