Top Stories
New Drivers For Test
Pressure is mounting to reduce test costs, while automotive is demanding more ability for circuits to test themselves. Could this unsettle existing design for test solutions?
Speeding Up The Design Process
As time-to-market pressure mounts, companies are looking at different ways to reach their end goal.
Making Verification Easier
Verification IP is finding new uses to speed up and simplify verification particularly when coupled with emulation technology.
What’s Next For UVM?
The ‘U’ in UVM was meant to be for ‘Universal’ but the notion of universality needs to be updated if it is to stay relevant.
Blogs
Editor in Chief Ed Sperling predicts China and other big players will wait until the price of borrowed capital increases before making big moves, in More Consolidation Ahead.
Technology Editor Brian Bailey contends EDA has been underpaid for so long that the necessary levels of investment have not been made in tools designers need today, in Time To Pay The Piper.
Cadence’s Frank Schirrmeister considers the value of models in software development and architectural analysis, in Models Are Dead? Long Live Models.
Synopsys’ Pat Sheridan examines how background power consumption impacts the energy efficiency of an SoC, in Time For A DDR Background Check.
OneSpin’s Dave Kelf finds practical experience and new techniques in abundance at the recent TVS event, in Formal Has Its Day.
NetSpeed Systems’ Rajesh Ramanujam explains how HG Wells’ observations apply to dynamic workloads in SoC applications, in Adapt Or Perish: A Unified Theory Of Coherency.
Mentor Graphics’ Paul Musto digs into AMS design challenges with high-speed analysis, in Advanced Analog And Mixed Signal Design Continues Pushing The Design Envelope.
ARM’s Matt Sealey drills down into how to improve the control flow and data management when writing and observing code, in Why Instrumentation Isn’t Optional.
Aldec’s Krzysztof Szczur discusses why it’s no longer one or the other, in To Emulate or Prototype?
