Special Report
CEO Outlook: Chip Design 2017
Political uncertainty, tempered optimism, continued consolidation, and concerns about capacity.
Top Stories
What’s Missing In Advanced Packaging
When it comes to multi-board and multi-chips-on-a-board designs, do engineers have all the tools they need?
Tools For Heterogeneous System Development
Final in a series: The amount of software that interacts with hardware is increasing, and no longer can applications ignore the execution platform. What is EDA doing to help?
Reflecting Back On 2016
How last year’s predictions for tools, design and manufacturing panned out over the past 12 months.
News
EDA, IP Up 7%
Strong growth numbers in Q3 reflect overall semiconductor market strength, complexity of design.
Blogs
Editor In Chief Ed Sperling contends that mathematics has confused everyone since the dawn of civilization, in So Much For Pure Science.
Technology Editor Brian Bailey finds no end to things people think are worth patenting, in Crazy Christmas Patents.
Mentor Graphics’ Geir Eide shows why cell-aware diagnosis is useful for finding problems at leading-edge nodes, and for everyone else, in Transistor-Level Defect Diagnosis.
Synopsys’ Malte Doerper compares virtual prototyping to cooking because it can be learned by focusing on a few key elements, in Virtual Iron (Chef).
Cadence’s Frank Schirrmeister predicts that verification will become a whole lot smarter next year, in Top 7 Verification Trends For 2017—Changes In The Game Of Ecosystems.
Arteris’ Kurt Shuler explains how to keep your skills up to date to avoid missing automotive opportunities, in ISO 26262 Functional Safety Training Resources.
Aldec guest blogger Espen Tallaksen examines how to verify programmable chips faster, with better quality, and at no extra cost, in FPGA VHDL Verification.
eSilicon’s Mike Gianfagna uncorks a design technology wish list, in All I Want For Christmas…
OneSpin’s Dave Kelf provides a classic logic puzzle for the holidays, in Solving Einstein’s Riddle Using Formal Verification.
