Top Stories
New AI Processors Architectures Balance Speed With Efficiency
Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.
AI’s Role In Chip Design Widens, Drawing In New Startups
Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.
Edge Devices Require New Security Approaches
More attack points and more valuable data are driving new approaches and regulations.
Defining The Chiplet Socket
The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?
Developing Workflows To Streamline System-Level Design
EDA tool providers will serve as powerful allies for customers to develop and implement workflows, and to show them what’s possible.
As EDA Processes Becomes More Secure, So Do Chips
Researchers and engineers are working on increasingly secure processes in the EDA workflow, but they add to the cost.
Focus Shifts To Application-Specific Workloads
System-level design is in constant flux, making it difficult to set standards or develop flows and tools.
Blogs
Technology Editor Brian Bailey contends that systems companies need to work out where they add value with chiplets and what they should outsource, in A New Generation Of 7400 Socket.
Eliyan’s Ramin Farjadrad shows how to minimize the number of wires between dies with networking technology that allows data to move in both directions, in Simultaneous Bi-Directional Signaling: A Breakthrough Alternative For Multi-Die Assemblies.
Siemens EDA’s Neel Natekar zeroes in on how to reduce over-design and determine exact margins with high-fidelity full-chip ESD verification, in Design Optimal ESD Protection With Context-Aware SPICE Simulation.
Arteris’ Insaf Meliane explores a systematic approach to managing the intricate connections between numerous IP blocks, in Streamlining Complex Semiconductor Designs With IP-XACT-Based Structured Assembly.
Alphawave Semi’s David Kulansky outlines how linear pluggable optics and sophisticated SerDes offer a path to higher bandwidth with less power and latency, in PCIe Over Optical: Transforming High-Speed Data Transmission.
Keysight’s Michele Robinson-Pontbriand explains why 6G represents a major shift in how the communications industry can approach sustainability, in Energy Efficiency As A Native Network Attribute Through 6G.
Cadence’s Frank Ferro digs into memory options and how to get high bandwidth while still using standard packaging and PCB technology, in GDDR7: The Ideal Memory Solution In AI Inference.
Synopsys’ Stelios Diamantidis shares insights from the Hot Chips conference, illustrating how ecosystem players are adapting to the challenges and opportunities of the AI era, in Accelerating The Pace And Precision Of AI Chip Innovation.
Sponsor White Papers
Chiplets and the Early Adopter’s Dilemma
A novel PHY may be the answer to the packaging question.
Enabling Efficient Multi-Die Design Implementation and IP Integration
Integrate dies, and co-optimize thermal and power integrity to ensure design feasibility and accurate signoff for system-level effect.
Wire Bond Electrical Structural Test Methodologies
Capture wire bonding defects in molded integrated circuits (IC) in microelectronics.
Making Cache Coherent SoC Design Easier with Ncore
Create more scalable heterogeneous cache coherent systems.
Intel and Cadence Collaboration on UCIe: Demonstration of Simulation Interoperability
A UCIe case study.
Ready For Curvilinear: New Innovations For Resistance Extraction
How to predict circuit behavior in designs with unconventional shapes.
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