Top Stories
AI Drives Re-Engineering Of Nearly Everything In Chips
Complexity, uncertainty, and lots of moving pieces will challenge the semiconductor industry for years to come.
New Ways To Improve EDA Productivity
A multi-faceted approach is required to deal with growing complexity and a shortage of engineers.
Analog Creates Ripples in Digital Verification
While analog and digital verification efforts have been essentially separated, closer integration is resulting in a rethinking of standards.
AI Agents Need Goals
AI cannot optimize unless it can measure progress towards goals, but defining those goals is not easy, especially when looking at the entire development flow.
Video
What’s Changing In SerDes
Faster data movement in AI systems comes at a cost.
Opinion
Technology Editor Brian Bailey looks at issues stemming from AI software evolving much faster than the hardware, development and verification tools, and power sources, in Tape-Out Failures Are The Tip Of The Iceberg.
Sponsor Blogs
Arteris’ Andy Nightingale details how NoCs can provide a structured and scalable approach to transporting data between the many IP blocks in a chip, in Data Movement Is The Energy Bottleneck Of Today’s SoCs.
Synopsys’ Paul Carzola looks at the benefits of automating repetitive steps with proactive management to measure efficacy and maximize efficiency, in AI-Driven Verification Regression Management.
Siemens’ Jonathan Muirhead explains how to reduce design iterations and improve product quality by moving critical checks earlier in the design cycle, in Reap Rewards With Shift-Left Pattern Matching For Custom And AMS Designs.
Cadence’s Geeta Arora shows how to capture a granular view of link operation using specialized data packets designed to carry debug information, in NOP Flit Payload: A Dedicated Debug Channel.
Keysight’s Roberto Piacentini Filho digs into high-speed digital design challenges, EDA tool capabilities, and software integration benefits, in What Is Electronic Design Automation And Why Do You Need It?
Axiomise’s Ashish Darbari shows a way to detect and eliminate underutilized components, in How To Optimize Silicon Utilization To Improve PPA.
Sponsor White Papers
Multi-Die Design Start Guide
Advantages of multi-die designs and guidelines on addressing essential upfront considerations.
Accelerating SI/PI Signoff: A Shift-Left Approach to PCB Design
How in-design analysis helps engineers catch and fix SI/PI challenges early, saving time, reducing risks, and ensuring first-pass success.
Combination of Coherent and Non-Coherent NoCs Facilitates Cutting-Edge SoC Design
A case study on the use of highly configurable NoC tools that could generate NoC interconnect.
Modeling Flux-Quantizing Josephson Junction Circuits
Methodology for constructing flux-quantizing circuits.
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