Top Stories
Strain, Stress In Advanced Packages Drives New Design Approaches
Heterogenous integration is pushing chip and package designers to consider multi-physics effects as early as the initial architectural planning stage; new tools may be needed.
Improving Verification Performance
Verification tools are getting faster and capacity is increasing, but they still can’t keep up with the problem space. Verification is crossing more silos, requiring expanded skill sets.
SLM Evolves Into Critical Aspect Of Chip Design And Operation
Silicon lifecycle management applications and techniques are gaining traction as chipmakers figure out how to use them more effectively.
Chip Companies Play Bigger Role In Shaping University Curricula
Design and AI companies are using a range of tools to help graduates become productive more quickly. Some are feeding their requirements directly to university.
RISC-V Profiles Help Conformance
More than just the processor needs to be defined for standard operating systems. Profiles help a little, but still not enough.
Tech Talk Videos
The Evolution of HBM
From 2.5D to AI everywhere.
Distributed Voltage And Frequency Scaling Gaining Traction
More data to process with fewer available knobs to turn are boosting demand for this technique.
Opinion
Technology Editor Brian Bailey looks at which EDA stories got the most traffic over the past year and why, in Design And Verification Issues In 2024.
Sponsor Blogs
Cadence’s Sanjeet Kumar digs into a scalable I/O technology specifically designed for inside-the-box asymmetric USB applications, in Introduction Of High Bandwidth Embedded USB2v2 (eUSB2v2) Standard.
Alphawave Semi’s Archana Cheruliyil shows why a custom implementation of HBM can be a performance differentiator that justifies its complexity, in Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 3.
Keysight’s Gabrielle Duncan examines the behaviors of materials and components under actual operating conditions, in Why Circuit Designers And Test Engineers Need Impedance Analyzers.
Siemens’ Jeff Wilson zeroes in on how to deal with IR drop and electromigration early in the design process, in Enhancing Power Reliability Through Design-Stage Layout Optimization.
Arteris’ Andy Nightingale looks back on the year’s advancements in modular scaling, cache coherence, and hardware/software integration, in 2024 Set The Stage For NoC Interconnect Innovations In SoC Design.
Synopsys’ Vamsi Thatha focuses on the benefits of advanced parasitic extraction, power analysis, and physical checks in multi-die designs, in Achieving Successful Multi-Die Signoff.
Alphawave Semi’s Archana Cheruliyil notes the key elements and considerations involved in implementing a 2.5D HBM design, in Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 2.
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