Special Report
Programmable Chips Evolve For Shifting Needs
Designers are utilizing an array of programmable or configurable ICs to keep pace with rapidly changing technology and AI. DSPs remain key.
Top Stories
When To Move To Multi-Die Assemblies
Multiple factors are involved in deciding when and whether to disaggregate a planar SoC.
2025 – A Year Of Change And Anticipation
Unexpected change rewards those who are quick to adjust, but all aspects of a system must be adjusted to keep growth going.
Opinion
Tracking Your Preferences
What did you want to read about in 2025? While most of it was fairly predictable, there were some surprises.
Sponsor Blogs
Synopsys’ Frank Schirrmeister targets verification platforms that can scale with industry demands and support emerging use cases, in Software-Defined Hardware-Assisted Verification: Scaling To Quadrillions Of Cycles For Verification In The AI Era.
Cadence’s Reela Samuel breaks down how advanced packaging technologies are reshaping stacked die, in 3D-IC Market Outlook: Technology Roadmaps, Readiness, And Design Implications.
ChipAgents’ Mehir Arora and Zackary Glazewski discuss an agentic AI-based approach for end-to-end bug resolution using both error logs and waveforms, in Autonomous ASIC Root Cause Analysis.
Movellus’ Hans Yeager and Aakash Jani explain why the voltage set at the regulator is rarely what the transistors actually see, in Setting Vmin With Transistor-Level PDN Telemetry.
Siemens EDA’s John Ferguson shows why it’s essential to combine sign-off accuracy, iterative feedback, and intelligent automation, in Managing Complexity: Evolving Approaches To Design Rule Checking In Modern IC Design.
Keysight’s María Castillo explains how to ensure data moves smoothly across multiple disciplines, tools, and globally distributed teams, in Transforming Data Management In EDA: Preparing For The AI Era.
Sponsor White Papers
PCIe Design Guide – Q&A (Gen 4, 5, 6) – Part 2
Part 2: A deep dive into simulation, validation, and compliance, answering 30 advanced, real-world questions engineers face when bringing PCIe-based systems to life.
Minimizing Design Risk: Rapid Feasibility Exploration For Multi-Die Designs
How rapid, comprehensive feasibility exploration enables designers to confidently evaluate IR drop, electromigration, and thermal impacts early in the design process.
The Power Of Shift-Left DRC Verification With Calibre nmD Recon
Speeding up DRC with maximum check coverage and minimal hardware.
Accelerating Semiconductor Innovation Through Machine Learning-Driven Modeling
Using AI and machine learning as transformative solutions for semiconductor device modeling and parameter extraction.
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