Special Report
First-Time Silicon Success Plummets
Number of designs that are late increases. Rapidly rising complexity is the leading cause, but tools, training, and workflows need to improve.
Top Stories
Challenges In Managing Chiplet Resources
The chip industry is exploring multiple avenues for simplifying multi-die integration, but difficulties remain for optimizing designs.
Digital Twins For Design And Verification Workflows
Can we model the chip development flow so AI could optimize it?
Verification Experts Vs. Generalists
The increasing complexity of design is driving specialization and innovative approaches in verification — and some interesting arguments.
The Evolving Role Of AI In Verification
Semiconductor verification is changing to integrate AI with human expertise.
Tech Talk Videos
Scenario Coverage In Formal Verification
As complexity of designs increases, so does the need for coverage in context.
Optimizing Data Movement In SoCs And Advanced Packages
Managing on-chip data is becoming more challenging in the AI era.
Opinion
Technology editor Brian Bailey notes that the founders of EDA are retiring, and perhaps it’s time that EDA headed off in a different direction, in Times Are Changing For EDA.
Sponsor Blogs
Siemens’ Harry Foster explains why the industry needs a fundamental shift in how verification is approached, in How AI And Connected Workflows Will Close The Verification Bottleneck.
Cadence’s Paul Graykowski delves into optical technology and alternate ways to verify the functionality of a full multi-chip system, in High-Speed High-Capacity Mixed-Signal Simulation Of Silicon Photonics.
Alphawave Semi’s Tony Chan Carusone digs into chiplets and how they can help maintain the annual cadence of hardware upgrades that AI scaling demands, in Unleashing AI Potential Through Advanced Chiplet Architectures.
Keysight’s Hwee Yng Yeo discusses 6G challenges and why emulation is crucial for testing the performance of 6G systems in real-time channels and networks, in Innovating For 6G.
Arteris’ Andy Nightingale shows why manual design approaches can struggle to minimize wire length as design complexity increases, in Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs.
Sponsor White Papers
Virtualizer Native Execution Accelerates Software Defined Product Development for Arm Solutions
Advancements in virtual prototyping with near native execution performance.
Dynamic Characterization Of A Power Semiconductor Bare Chip
Challenges of performing dynamic characterization on a bare chip, as well as technologies to help.
Accelerate And De-risk RISC-V- Based SoC Designs
Speed up the integration of RISC-V based systems with seamless connections between processor cores or clusters and IP blocks from multiple vendors.
Allegro X AI for Generative System Design
Leverage GenAI and search to synthesize PCBs directly using physics-based analysis and high-level design goals.
A Novel Approach For HW/SW Co-Verification
Leveraging PSS to orchestrate UVM and C tests.
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