Top Stories
Optimizing Data Movement
Problems and solutions for improving performance with more data.
A Balanced Approach To Verification
In the past, simulation was the only tool available for verification, but today there are many. Balancing the costs and rewards is not always easy.
Executive Outlook: Chiplets, 3D-ICs, and AI
Trouble spots, and some fixes, for the next wave of high-performance semiconductors.
More Data, More Redundant Interconnects
Circuits are being pushed harder and longer, particularly with AI, speeding up the aging of data paths. Photonics adds its own complications.
From Tool Agents To Flow Agents
The industry has already demonstrated gains using AI in tight iteration loops, but how does that evolve to cover larger portions of the development flow?
Future-Proofing AI Models
The rate of change in AI algorithms complicates the decision-making process about what to put in software, and how flexible the hardware needs to be.
Video
Optical Interconnectivity At 224 Gbps
Pros and cons of replacing copper with optical in data-intensive AI systems.
Speeding Up Die-To-Die Interconnectivity
Just adding more or thicker wires to a design isn’t sufficient with chiplets.
Opinion
Brian Bailey queries whether large EDA companies are ignoring some of the benefits of the Design Automation Conference, as its funding shrinks, the event shortens, and attendance drops, in The DAC Valuation.
Sponsor Blogs
Siemens’ Shetha Nolke examines the causes of mechanical failures in 3D-ICs, in Addressing Stress In Heterogeneous 3D-IC Designs.
Synopsys’ Larry Lapides outlines a plan for multiple complementary verification methodologies for different levels of processor integration, Closing The RISC-V Verification Disconnect.
Keysight contributor Michelle Clancy Fuller examines the impact of disaggregation on verification, in Mastering Chiplet Design.
Cadence’s Vanessa Do explores the benefits of CXL architecture in memory expansion and sharing for AI, while ensuring data consistency within the fabric, in Boosting AI Performance With CXL.
Arteris’ Insaf Meliane explains how to eliminate hardware-software mismatches and ensuing design re-spins of complex SoCs, in CSR Management: Life Beyond Spreadsheets.
Alphawave’s Shivi Arora and Sue Hung Fung explain how to share data efficiently between CPU cores, accelerators, and other components, in Accelerating Scalable Computing.
Sponsor White Papers
SoC Power Delivery Network (PDN) Telemetry And Applications
Why PDN visibility is critical to each stage of the silicon lifecycle and its relationship to power, performance, and in-field uptime.
AI Infrastructure: Optimized For Model Training
Testing AI infrastructure performance, ensuring networks can handle demanding AI workloads without becoming bottlenecks.
Mastering AI Chip Complexity: Your Guide to First-Pass Silicon Success
Navigating the transition from traditional monolithic architectures to multi-die and chiplet-based solutions.
Modernizing The Hardware / Software Interface – Life Beyond Spreadsheets
A scalable infrastructure that promotes a rapid, highly iterative design environment to specify, document, implement, and verify address maps for complex SoCs and FPGAs.
Agentic AI, Multi-Block Multi-User SoC Design Platform
Use the most advanced AI technology to optimize an entire SoC within a single platform with a small design team.
Thermo-Mechanical Stress On Active Chiplets In A 3D-IC Heterogeneous Package Assembly
Addressing stress-related issues early in the design cycle using chip-package co-design and co-optimization.
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