Special Report
Top-Down Vs. Bottom-Up Chiplet Design
Third-party chiplets are hitting the market as chiplet models evolve. Who’s calling the shots isn’t clear yet.
Top Stories
Slow Progress On Generative EDA
The dream may be to have generative AI write RTL, but text is only one of the necessary things AI must understand to help with many design and implementation problems.
How AI Is Transforming System Design
LLMs and machine learning are automating expertise in an aging workforce.
RISC-V’s Software Portability Challenge
A hardware-software contract is needed for software portability, but RISC-V is not yet defined well enough to know what that is.
Tech Talk Video
Scaling Performance In AI Systems
Tackling bottlenecks and improving time to market in complex designs.
Using Formal For RISC-V Security
Why microarchitectures and custom coding on low-cost chips are a growing source of concern.
Opinion
Technology editor Brian Bailey suggests any optimization problem must have a clear, unambiguous specification and a way to define the goodness of the solution, in Goal-Driven AI.
Sponsor Blogs
Arteris’ Andy Nightingale explains how mesh network topology ensures efficient communication between tiles, avoiding bottlenecks and allowing for parallel processing across the chip, in Scaling AI Chip Design With NoC Soft Tiling.
Alphawave Semi’s Archana Cheruliyil outlines the advantages and challenges of HBM and the quest to shrink the memory-performance gap, in Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 1.
Siemens’ Wael ElManhawy explores a shift-left methodology to perform LVS comparison earlier in the design flow, catching errors sooner and reducing the number of iterations required during sign-off, in How To Speed Up LVS Verification.
Synopsys’ Samad Parekh looks at the increasing level of integration and miniaturization in PMICs driven by trends in IoT, wearables, and consumer electronics, in Successful Design Of Power Management Chips.
Keysight’s Chaimaa Aarab highlights challenges around non-terrestrial networks, Wi-Fi 7, 6G, and the growing role of AI and ML in network optimization, in The Latest Wireless Industry Use Cases.
Cadence’s Steve Brown delves into chiplet-based architectures and how they address issues of design complexity and yield, while significantly reducing time to market and development costs, in Outlook 2025: Embracing Chiplets.
Sponsor White Papers
Why Silicon IP Has Become the Foundation of Modern SoC Design
IP and data management solutions for more effective SoC design.
The Xpedition Flow
Equipping enterprise engineering teams to handle complexities in electronics systems design.
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