Special Report
Partitioning In The Chiplet Era
Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.
Top Stories
Chiplets Make Progress Using Interconnects As Glue
Industry learning expands as more SoCs are disaggregated at the leading edge, opening the door to more third-party chiplets.
HW and SW Architecture Approaches For Running AI Models
Custom hardware tailored to specific models can unlock performance gains and energy savings that generic hardware cannot achieve, but there are tradeoffs.
RISC-V Conformance
Finding out if a processor implementation matches the specification is important, but conformance testing is currently not available.
Barriers To Chiplet Sockets
Perfection sometimes stands in the way of progress, and there is evidence this may be happening with chiplets. It may be time to slow down and make real progress.
Tech Talk Video
Working With Chiplets
What comes after HBM, and why that matters for future designs.
Data Routing In Heterogeneous Chip Designs
Challenges and solutions for working with multiple chiplets.
Globally Asynchronous, Locally Synchronous Clocks
Improving performance through better partitioning of data movement in complex designs.
Opinion
Degrees Of Freedom For Innovation
Technology Editor Brian Bailey contends that EDA startups of the future will look very different because they don’t have a choice.
Blogs
Siemens EDA’s John Golding shows how to use a signal integrity simulator to find the optimal interconnect topology and termination for a given situation, in Managing Reflections With Terminations.
Synopsys’ Aparna Tarde digs into die connectivity, splitting, and attachment for AI applications, ensuring interoperability, low latency, and real-time data movement, in Why 40G UCIe IP?
Arteris’ Andy Nightingale looks at the benefits of physically-aware and domain-aware NoCs, including low power, high performance, and scalability, in Reducing SoC Power With NoCs And Caches.
Alphawave Semi’s Shivi Arora and Sue Hung Fung explain why 6G will require new RF designs and chipsets capable of handling much larger amounts of data, in Revolutionizing High-Performance Silicon With Next-Gen Chiplets.
Cadence’s Nayan Gaywala delves into HPC subsystems and why CPU cores need to access shared data in an atomic fashion in a multi-core environment, in Locking When Emulating Xtensa LX Multi-Core On A Xilinx FPGA.
Keysight’s Allison Freedman outlines steps to enhance cyber defense training and why it’s essential to create realistic models of mobile networks, in Mastering Cyber Awareness: Training For The Digital Battlefield.
Eliyan’s Ramin Farjadrad takes stock of what’s needed to consistently move data at speeds required for AI systems, in UMI: Extending Chiplet Interconnect Standards To Deal With The Memory Wall.
Sponsor White Papers
Accelerate AI SoC Designs with NoC Tiling
Create modular, scalable designs by replicating soft tiles across the chip.
Early Architecture Performance and Power Analysis of Multi-Die Designs
Overcoming the challenges of multi-die designs.
Four Real-World Applications for Electromagnetic Simulation
Using EM simulation to accelerate and simplify your design workflow to create better designs.
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