Special Report
Using AI To Glue Disparate IC Ecosystem Data
Why the chip industry is so focused on large language models for designing and manufacturing chips, and what problems need to be solved to realize those plans.
Top Stories
RAG-Enabled AI Stops Hallucinations, Adds Sources
New GenAI method enables better answers and performs more functions.
Pressure Builds To Adopt Virtual Prototypes
Creating complex multi-chiplet systems is no longer a back-of-the-envelope diagram, but viable methodologies are still in short supply.
New AI Processors Architectures Balance Speed With Efficiency
Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.
What Comes After HBM For Chiplets
The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?
Sponsor Blogs
Technology editor Brian Bailey asks if EDA is meant to react to the needs of the industry, or anticipate its needs and develop ahead of the curve, in Reactionary Or Anticipatory?
Siemens’ Reetika and Sulabh Kumar Khare show how constraints generated by advanced data analytics can reduce manual setup and review efforts, in Accelerating Reset Domain Crossing Verification With Data Analytics Techniques.
Keysight’s Ben Miller provides an in-depth look at the high-speed data communication standard’s benefits and tradeoffs, and how it enabled today’s emerging technologies, in PAM4: Pulse Amplitude Modulation Explained.
Blue Cheetah’s Elad Alon discusses the three dominant chiplet product use cases emerging today — single-vendor, plug-and-play, and multi-vendor, in Enabling Innovative Multi-Vendor Chiplet-Based Designs.
Arteris’ John Min explains how NoCs reduce the number of physical connections needed, helping to alleviate congestion, lower power consumption, and simplify timing closure, in Managing Performance in Modern SoC Designs.
Cadence’s Shyam Sharma looks at the tradeoffs and insights for choosing and working with different DRAM DIMMs, in DDR5 UDIMM Evolution To Clock Buffered DIMMs (CUDIMM).
Axiomise’s Ashish Darbari and University of Southampton’s Ia Tsomaia discuss what’s nice to have and what’s essential when it comes to verification and simulation, in Corner-Case Bug Hunting for RISC-V.
Sponsor White Papers
Maximizing Coverage Metrics with Formal Unreachability Analysis
How to detect unreachable coverage formally and what to do about it.
Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization
New challenges as the PDN requirements of cutting-edge designs continue to evolve.
UMI Can Scale the Memory Wall
UMI to OCP as an extension to the BoW standard.
Accelerate Your Digital Transformation with ADS Python Automation
Three automation use cases for expanded transforming modern RF and high-speed design.
Signal Integrity Basics
eBook: Pre-requisites for successful high-performance electronic system design.
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