Top Stories
Why All Nodes Won’t Work
Cost of porting tools and IP will limit choices at partial nodes and create confusion at others.
IP And Power
How can power be optimized across an entire chip when most of a chip’s content comes from third-party IP?
New Issues In Advanced Packaging
The race is on to simulate thermal and electromagnetic effects.
Blogs
Editor In Chief Ed Sperling predicts that the revolution that started in mobile phones will continue in other devices, only much faster, in Exponentials At The Edge.
Executive Editor Ann Steffora Mutschler finds the combination of heterogeneous architectures and RISC-V is driving support for new tools, in Heterogeneous Hubbub.
Mentor’s Progyna Khondkar takes a deep dive into the foundations of PA static verification and the solution features used for its verification, in Power-Aware Intent And Structural Verification Of Low-Power Designs.
Synopsys’ Rita Horner shows how to successfully design systems with the new PCIe 5.0 interface, in 32GT/S PCI Express Design Considerations.
Fraunhofer’s Benjamin Prautsch and Torsten Reich observe that aggregating data is the basis of modern production systems, and it needs to be considered from system requirement to analog layout, in The Analog Design Gap.
Rambus’ Steven Woo points to different architectures to get around the memory bottleneck, in How AI Impacts Memory Systems.
ANSYS’ Allen Baker questions whether today’s vast and power hungry computational landscape is sustainable, in Energy Requirements And Challenges For IoT Autonomous Intelligence At The Edge.
Cadence’s Dave Stratman examines why design flows are so important for getting the low-power/high-performance benefits of the latest nodes, in By The Power Vested In Me, I Now Pronounce You (The SoC Designer)…
Arm’s Ian Forsyth looks at the role of efficient inferencing in moving machine learning forward, in Intelligence At The Edge Is Transforming Our World.
