Why All Nodes Won’t Work

Cost of porting tools and IP will limit choices at partial nodes and create confusion at others.

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A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it’s good to have choices, it’s not clear which or how many of those choices are actually good.

At issue is which IP will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a variety of types of noise, and which versions were tested with which version of the manufacturing process for nodes and “nodelets.” Most of these new partial nodes have not been clearly defined yet. As a result, it’s too early to tell which type of transistor will be used, which will affect both gate leakage and dynamic power density, how much additional patterning will be required, and how that will affect neighboring IP and other components.

“There are now numbers and different names all over the place,” said Ranjit Adhikary, vice president of marketing at ClioSoft. “The question is what is the PPA for each of these. PPA has always been the basis of deciding which IP is right for your design. But now you need to look at which foundry offers it and which node is supported. For each IP, there may be different memory or cache, and that varies by foundry, by category, and by process node.”

Foundry plans and where they are today. Source: Analysts, Foundry Reports/Semiconductor Engineering

But there are multiple flavors of all the major process nodes, and multiple partial nodes ranging from 22nm all the way down to 3nm. That is prompting questions about what IP is available, whether it has been fully characterized and tested for each node, and whether it will be supported for the amount of time required for different end markets. This hasn’t been a problem for mobile devices, which have dominated the chip world over the past couple decades with relatively short product cycles, but it’s a completely different story for industrial and automotive applications, where devices need to be supported for decades.

“We’ve never seen so much node proliferation from foundries,” said Navraj Nandra, senior director of marketing for the DesignWare Analog and MSIP Solutions Group at Synopsys. “We’ve got node names from 18nm down to 1nm. But it requires a commitment by management to invest in a node. They want to see if hard IP is available, and for that you need an SoC to be available because you really want to see a silicon test report of IP working in a new node. That requires an investment by the IP supplier, too. So the foundry may find something slightly better from a timing perspective and an ROI perspective, such as a high-speed memory interface or something that is HBM-based. But you also can spend a ton of money here and not actually make any money.”

That seems to be a consistent message from IP developers. Rather than support every node, as they did in the past, they are trying to assess which nodes are likely to generate enough volume to generate a reasonable return on invested capital. Effort does not always turn into profits, particularly at advanced nodes, and a wrong choice can be costly.

“We all know that the newer process geometries are more of a guide as to what the process capabilities are (transistor density and power/speed tradeoffs) than to any actual physical dimension of the process,” said Marc Greenberg, group director for product marketing, DDR, HBM, flash/storage and MIPI IP at Cadence. “The industry standard to date has been to indicate key differences in processing-for example, SiON (silicon oxynitride) versus high-k/metal gate, EUV or not-with different letter or symbol suffixes to the process. But that may eventually become new nodelets instead of new suffixes. At the 28nm node, we saw a lot of variants of the 28nm processes that were generally incompatible with each other. That created a lot of work for the IP industry to cover all of these process node variations. We also saw some of the early finFET nodes have some difficulty taking off, which was more work for the IP industry that didn’t necessarily convert into sales.”

What is a nodelet?

Much of the confusion around nodelets is based on marketing terminology. Numbers have blurred to the point where no one is quite sure what the numbers really signify. What TSMC and Samsung call 5nm is actually 7nm for Intel, GlobalFoundries and Imec, and the same applies for 10/7nm and 5/3nm. On top of that, there are different versions of these nodes, based on low power or high performance or cost, each of which can have its own unique twists.

“The thought process in an established node is that if it’s in production, then you can optimize that node,” said Synopsys’ Nandra. “So you have 28nm and you know it works well and defect density is in a solid percentage. To improve that, you squeeze it a little, give it a new name like 22nm. But that doesn’t mean that it has a 22nm gate length. You’ve done something to give it better density. That shouldn’t be a big change for the IP community. But when it comes to high-speed versions, with extraction, simulation, resistances, capacitance and inductive relationship of packages, the impact of transistors as they have gone through optical shrink, all of that creates a big amount of re-working. You need a complete revalidation of the IP. Post-layout parasitic extraction can be quite a challenge. Or you need to complete a new test chip just to make sure you have not missed anything.”

Until the finFET era, foundries would follow Intel’s “Tick-Tock” strategy of nodes and half nodes. But after 28nm, node numbering began splintering into numbered slices that may or may not pan out, in large part because there may not be enough IP choices available to make them viable. While the big IP vendors will follow, at least for now, it’s not clear whether the rest of the industry can keep up.

“The 16/14nm finFET node is quite stable at the moment,” said Cadence’s Greenberg. “The 12/11nm nodelet is also getting good support from foundries. The guidance we receive from foundries is that it should be an ‘easy’ IP port from 16/14nm to 12/11nm. However, in some cases we have taken the step of producing and characterizing new IP testchips for those nodes. Some foundries are supporting the 10nm half-node and its 8nm nodelet, which we’re supporting with select IPs. At 7nm, we have a strong node that Cadence is broadly supporting with the latest advanced technology IP. It’s still early to tell if there will be a broadly supported 6nm nodelet, or whether the industry jumps to 5nm.”

Nandra noted that the effort may be more costly than IP developers expect. “Customers, if they can, will request a characterization report based upon silicon. And if there is a strong analog/mixed-signal piece, the customers are even more conservative. They want to see more silicon.”

The devil in the growing number of details
For 28nm and beyond, there appears no end to how far nodes will scale. Current estimates are somewhere in the neighborhood of 1.2 to 1.3nm, although exact number may change depending upon the types of transistors-gate-all-around FETs versus finFETs, for example-the introduction of lithography options such as directed self-assembly and high-NA EUV to extend device scaling, and advances in metrology, etch and deposition.

“7nm technologies are under development, and 5nm as well as 4nm have been announced,” said Roland Jancke, head of the department for design methodology forĀ Fraunhofer’s Engineering of Adaptive Systems Division. “In order to increase the performance of such a technology, the integrated devices are extremely optimized. As a result, a vast number of individual device types appear within a technology node, such as I/O devices, core devices, pull-up and pull-down devices, along with several threshold voltage versions of a device. This tendency dramatically increases the effort for technology characterization, qualification, and model development, which needs to be repeated after each process change.”

Moreover, these devices are increasingly sensitive to physical factors such as temperature and noise. Threshold voltages respond differently at different temperatures, and that sensitivity increases with each node shrink. The result is a need for much more detailed characterization than in the past.

“We made a shift on high Vt band and couldn’t catch the problem initially,” said Craig Hampel, chief scientist at Rambus. “So now if we have high Vt, we increase the level of characterization. Our characterization has increased almost four times in the past couple years with the move to 16nm.”

The problem gets worse at each new node after that, too. But increased characterization is no longer just a lower-node problem. There are many variations of older-node processes, as well, and there are more use cases involving safety and reliability that require more characterization even at older nodes.

“For mixed-signal technology nodes in the range down to 110nm, there is a huge diversity of flavors within a given node,” said Fraunhofer’s Jancke. “There are often individual versions of a technology for ultra-low power, for high power, as well as for high voltage, for RF and optical applications, for MEMS devices, and others. On the other hand, designers tend to integrate several parts of an SoC into a single silicon die, which led to the development and increasing interest in combined technologies, such as BCD processes for power ICs.”

That also makes it harder to assess which IP will work best because that IP needs to work with other IP. All of this can affect time to market, overall cost, as well as power/performance. And perhaps even worse, it can limit the functionality of a device if there are fewer options available.

“There are a lot of questions that need to be answered with IP,” said ClioSoft’s Adhikary. “If you take IP from a 9nm node and move it to 5nm because you need more performance, how much area do you gain by doing that? It may take three to four months to develop IP for a new node. Are you really getting benefits in area and performance, though? And if you’re doing multiple tapeouts a year, what version of the IP are you using? If someone else uses that IP, are they working with the same PDK libraries? If you’re integrating IP with other IPs, you really need to be sure you’ve got the same versions of PDKs. We’re seeing a lot more attention now to what version of PDK and what version of libraries are being used. There are more and more details you need to keep track of.”

From the IP developer’s standpoint, this is problematic, as well. “The effort difference is apparent going to newer versions of technologies,” said Synopsys’ Nandra. “It takes longer to develop IP at 7nm or 10nm than at 14nm or 28nm, and that effort is typically two to four times what was originally scoped.”

Conclusion
All of this gets more complicated with new nodes, nodelets and node naming conventions. The foundries have stepped up their efforts to provide more data, and IP vendors are doing much more characterization than in the past because tolerances become tighter at each new node and nodelet.

“Everyone has learned from the 28nm era, and while there will always be advances in processing during the lifetime of a node, the foundries have gotten better about giving IP providers earlier indications on those and guidance on the differences between the base process and its variants,” said Greenberg. “In some cases, that allows us to target mixed-signal IP development at a node and its nodelet, or multiple suffix processes, from the same IP development. When the foundries are able to communicate those plans to us far enough in advance, it helps us to provide a wider range of IP and ultimately helps to keep the cost down.”

But at least for the foreseeable future, managing node names, numbers and IP versions will become more difficult, to say the least. There are simply too many options and potential interactions, and far too many ill-defined or still undefined moving parts.

Related Stories
Is 7nm The Last Major Node?
Technical issues increase, costs go up, and not all markets will benefit.
Nodes Vs. Nodelets
Growing number of process options is creating confusion across the semiconductor industry.
New Nodes, Materials, Memories
What chips will look like at 5nm and beyond, and why the semiconductor industry is heading there.



4 comments

Richard Trauben says:

The most significant scale factors are contacted metal pitch at layer 1 and 3,Junction cap and I-off/I-on. LEF (library exchange format) should not be the prime directive unless reductions linearly scale with gate density.

eli says:

is intel shipping 14nm to someone? they have not reported any production sales. same question with umc.

Bruce says:

Seriously? Intel has shipped well over a billion units on their 14nm (Broadwell, Skylake, Kaby Lake, Coffee Lake, Knights Landing, Knights Mill, etc..)

John H says:

Global foundries is ramping 12nm; it’s pretty clear we’ll see a real launch of Zen+ in just a few weeks. It’s almost production.

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