New Nodes, Materials, Memories

What chips will look like at 5nm and beyond, and why the semiconductor industry is heading there.


Ellie Yieh, vice president and general manager of Advanced Product Technology Development at Applied Materials, and head of the company’s Maydan Technology Center, sat down with Semiconductor Engineering to talk about challenges, changes and solutions at advanced nodes and with new applications. What follows are excerpts of that conversation.

SE: How far can we push device scaling and what sorts of problems are you seeing?

Yieh: There are traditional Moore’s Law scaling issues at the most advanced nodes, and now we have new challenges with the expansion of device types. For example, there is fragmentation of memory technologies with the emergence of STT-MRAM and 3D XPoint memory. So there is no shortage of challenges in enabling advanced performance, and all of them require new materials.

SE: Where does ruthenium fit in?

Yieh: That’s one of the many materials we’re investigating.

SE: Why is that being looked at for interconnects?

Yieh: We’re working to improve the resistivity and gap fill. But the interconnect is only one piece of the scaling challenge. The contact and metal gate in the transistor area are also problematic with the move to smaller CDs (critical dimensions). A challenge the industry is dealing with is how to continue scaling the resistance and capacitance in various areas. From the transistor standpoint there are also many materials being investigated to improve the gate stack metal work function, or the channel mobility performance. And on top of that, with the EUV delay, different patterning schemes are needed to shrink small feature CDs. But alignment and overlay errors need to be overcome. New patterning material deposition schemes combined with selective etching are required to solve these issues. And the ultimate solution to reducing edge placement error issues is selective deposition, where materials are deposited precisely where they are needed to simplify and enable self-alignment.

SE: What kinds of issues are you seeing with selective deposition?

Yieh: Selective deposition is very challenging. It’s like trying to control where each snowflake should land during a blizzard. How do you make sure the snow only covers the rooftop and not the street? The ability to use materials engineering to define the different features is critical, and something that we are focused on at Applied.

SE: Logic seems comparatively straightforward, even though it’s difficult. But there are a lot of other variables that aren’t so obvious, right?

Yieh: Yes, scaling is not just about shrinking the CD. It’s also about the design and materials engineering techniques. An example of design for scaling is bringing the gate contact on top of the active gate. New materials and integration schemes are being developed for both performance and scaling. An example is scaling SRAM. At 5nm we see STT-MRAM being integrated for large cache to reduce chip size. That requires significant materials engineering attention to form the magnetic-tunnel-junction stacks by PVD, and then you need to etch those nonvolatile materials into pillars. So now a memory component is adding new materials to enable logic chip scaling.

SE: Memory constitutes a huge portion of these chips. How much can you reduce that area?

Yieh: Using STT-MRAM to replace large cache SRAM can shrink the area by 40% and free up a lot of valuable chip real estate. And being a nonvolatile memory in close proximity to the logic, it results in faster computation and energy savings.

SE: Let’s step back a bit. The markets for technology are fragmenting by application. We’re seeing growth at older nodes for things like IoT. But some of the huge growth markets will be in different areas such as artificial intelligence and machine learning, which require leading-edge logic. What are the issues there and how do they fit into your world?

Yieh: New compute and memory architectures and system-level design schemes are creating different types of challenges, which impact processing and memory. What’s important is to make sure the latency is improved. We’re focused on enabling these inflections. In the past, we only looked at logic, DRAM and NAND. Now there is storage-class memory. And now there are all these sensors–in particular, growing demand for image sensors for mobile devices, cars and surveillance applications. Image sensors used to be legacy technology without much innovation. Today, customers are trying to figure out new ways to improve the image quality and efficiency.

SE: Let’s switch to DRAM. Isn’t this is the ultimate plumbing problem?

Yieh: Yes, and customers are talking about further extending DRAM with different materials to improve bit-line resistance and parasitic capacitance. Similarly, in other memory devices such as phase-change memories, challenges in optimizing material systems for enhanced performance are critical.

SE: Phase-change technology can be used in neuromorphic computing, as well, right?

Yieh: Yes, we see people looking at different types of memory, including phase-change memory technology, to do neuromorphic computing.

SE: So what happens when you scale some of these new materials?

Yieh: New materials will have new performance metrics. For example, low-thermal-budget processing is a growing requirement that needs innovation because temperature directly impacts how all of these new materials behave. If the temperature for the materials system is too high, you may not get the switching you want. You have to get the film structure to where you want it, and then make sure it continues to behave in the desired way with subsequent processing.

SE: That doesn’t sound easy.

Yieh: It’s a very interesting time for materials and materials engineering. For instance, there are a couple different ways to do a vertical channel. One way is to put it down and etch it. Another is figuring out how to fill or grow it. Which way is better? Using ALD to fill or PVD and etch? Applied has the full equipment toolbox to investigate which path is better. At the Maydan Technology Center (MTC), we work to test and optimize various methods and validate them through physical and electrical testing. We build short-loop test vehicles. So we can build 14nm finFET test vehicles and can go down to 5nm with dual damascene to do electrical testing. We have a STT-MRAM test vehicle at 130nm pitch going down to 80nm, just to name a few. These capabilities allow extensive in-house learning.

SE: How many companies are going to be able to stay on this road map for device scaling? It’s getting very expensive.

Yieh: Agreed, but if you look at what is coming, it isn’t necessarily about small geometries. It’s about managing increasing complexities. Mobile phones still need small geometries for high performance and low leakage. Many people thought DRAM scaling would stop, too, but it continues to scale. These advancements don’t just happen, either. People keep at it. It’s amazing how many smart people are in this industry.

SE: Are there any other materials we haven’t heard about, other than some of the III-V classes?

Yieh: The number of elements in the periodic table being investigated and used today continues to expand. Each element and combinations of elements have specific properties that can enable new devices—for example, germanium-antimony-tellurium.

SE: You also want to know what will be needed in terms of equipment, right?

Yieh: We always have to look ahead. A few years ago, our customers discovered edge placement error would be a challenge. Alignment and overlay are difficult. We started looking at selective deposition and multi-color patterning as solutions to these challenges. Selective deposition uses different process technologies. Patterning schemes may require dielectric on dielectric, or dielectric on metal, or metal on metal. Multi-color is about different types of gap-fill materials. These new processes drive new equipment requirements, which give us many opportunities to provide value to our customers. Our equipment portfolio and capabilities give us an advantage in speed of learning.

SE: Is industry consolidation affecting R&D for you?

Yieh: No. Overall if you look at what’s occupying chipmakers, they’re ramping many new devices. There’s a considerable amount of activity taking place with companies designing AI and high-performance computing chips for specific workloads and different types of applications. Some of these require innovation breakthroughs that offer opportunities for new disruptive products. We see incredible opportunity in the emerging material and device inflections.

SE: Is it possible to get improvements in power and performance without shrinking, where instead you just change the materials?

Yieh: People are trying different things and focusing on the materials that have been investigated in the past. Many new ideas are being investigated and the speed of learning is accelerating.

SE: So what are you finding are the really tough nuts to crack, where maybe you’re heading down the wrong path?

Yieh: Every day we solve problems and find ways forward. Sometimes a solution will reach a point where a new approach is needed and that drives innovation. Solving complex challenges and doing what others think can’t be done is what inspires us. It’s a lot of fun.

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