Is 7nm The Last Major Node?

Technical issues increase, costs go up, and not all markets will benefit.


A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address.

At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather than one version of 10/7nm there are likely to be at least two or three (or more) iterations before the march begins down to 7/5nm.

Behind that slowdown is a growing disconnect between front-end design and back-end manufacturing, and there are several key reasons for that. First, node scaling has become so expensive that it’s no longer an automatic decision, even for the largest companies. Fabless chipmakers, in particular, are cautious about adopting expensive new tooling and methodologies because there are fewer high-volume market opportunities at leading-edge nodes. System vendors such as Apple and Samsung have begun building their own chips for mobile phones, and Google, Facebook, Amazon and Microsoft have begun designing their own chips for the cloud. The net effect is there are fewer high-volume markets available to recoup development costs for anyone else.

“For some applications, particularly mobile and cloud infrastructure, they have to drive performance,” said , president and CEO of Cadence. “They are racing down to 10nm, and they will continue down to 7nm and probably 5nm. But performance and price scaling are slowing down, and the cost is going up. There is no longer a huge performance difference. So for some companies, there is no longer a compelling reason to go down to 7nm. It depends on the product, the development cycle, and the delta of differentiation.”

Fig. 1: 7nm transistors packed below 30nm fin pitch. Source: IBM

Fortunately, a number of new markets have cropped up over the past 18 months. While none of those markets is expected to produce the billion-plus unit demand that is still possible in the mobile phone market, collectively they add up to even bigger market opportunities. This includes everything from automotive and medical electronics to chips for machine learning, artificial intelligence, augmented/virtual reality, IoT/IIoT, and more flexible server architectures that can be optimized as needed.

As a point of reference, SEMI said the automotive electronics market is expected to hit $280 billion by 2020, while medical electronics will hit $219 billion by 2024, according to Ajit Manocha, president and CEO of SEMI. Even more eye-popping, the $2 trillion electronics supply chain is expected to double over the next five years to $4 trillion. The semiconductor industry, meanwhile, is showing a healthy 12% growth, compared with the low-single digit growth that has marked the past decade.

“This is new,” Manocha said. “Wafer fab equipment is up 23%.”

Not all of those emerging markets require chips produced at the latest process node, either. Even in automotive, where the complex ADAS logic is being developed at 7nm, other chips being developed for the same car are being designed at older nodes. And with IoT/IIoT, many chips are being built using 200mm wafer processes, which makes them significantly less expensive to design and manufacture.

The short-term downside is this has created a huge capacity shortage. Six new 200mm fabs are under construction in China to alleviate this capacity crunch, and another two are under construction elsewhere, according to SEMI. At least part of this is due to an increased focus on opportunities at established process nodes. Depending on how these other markets fare, and how quickly they migrate to newer processes, it could have an impact on how quickly some of the technologies now in R&D are rolled out across the market.

A second reason for the slowdown is that it’s simply getting harder to design, inspect and test chips at advanced nodes. Physical effects such as heat, electrostatic discharge and electromagnetic interference are more pronounced at 7nm than at 28nm. It also takes more power to drive signals through skinny wires, and circuits are more sensitive to test and inspection, as well as to thermal migration across a chip. All of that needs to be accounted for and simulated using multi-physics simulation, emulation and prototyping.

This is bad enough in a smart phone, where a chip can be amortized across hundreds of millions or billions of devices. But as advanced-node chips find their way into autonomous vehicles and medical applications, they will be subject to even more scrutiny. In a car, a chip is expected to function within stringent operating parameters and in harsh environmental conditions for a decade or more.

“You’d ideally like to inspect everything, but it’s time and money and a large investment on metrology,” said Henk Niesing, director of applications product management at ASML. “For random defects, you can still be in that area. But in this way you don’t need to add more metrology. You can do more on the computation side.”

The third reason for a migration slowdown is that while much of the focus has been on lithography issues—multi-patterning, mask alignment, better resists, and EUV—that is only a piece of the puzzle. High numerical aperture EUV will likely carry lithography down to at least 2nm, and maybe even 1nm. But starting at 10/7nm, issues such as edge placement error are becoming more problematic. Contacts will require new materials. And line-edge roughness, which was always a manageable problem, is becoming much tougher to solve.

New focus on materials and numbers
The result is that a brute force approach to shrinking no longer works. One size does not fit all, and even in places where the same approaches can be applied, they now have to be weighed in the context of an end market, the supply chain, and even the availability of IP for a specific foundry’s process. Put simply, solving these issues is no longer a linear extension of what was done in the past, and this is evident in the growing emphasis on solving problems with materials—complex chemistries, some involving free radicals, different elements or combination of elements, some developed using a series of steps that involve heat, cold, pressure, or a vacuum.

For example, new tools and material types can address the edge-lacement error (EPE) issues. EPE basically is the difference between the intended and the printed features of an IC layout.

“You can use materials to solve edge-placement problems,” said Uday Mitra, vice president of etch and patterning strategy at Applied Materials. “It’s more cost-effective and it allows for more aggressive scaling, which in turn allows more relaxed design rules. Materials are cheaper than lithography, too, so you don’t have to use EUV for everything.”

Along with the materials, the industry is benefiting from the emergence of atomic layer etch (ALE). Unlike conventional etch tools, which remove materials on a continuous basis, ALE promises to selectively and precisely remove targeted materials at the atomic scale.

“The only way to get a cost-per-transistor improvement is with materials innovation,” Mitra said. “So even if the masks are misaligned, you can selectively etch out only some of the material. That way you don’t have to worry about edge placement, and the materials for placement problems continue scaling without yield problems.”

That’s one approach. Computational modeling is another, and the two are not mutually exclusive. If the front end of design is any indication, chipmakers and foundries need many more tools than they did in the past to get the job done. On the verification side, for example, multiple types of accelerated hardware are being used to improve reliability. On the manufacturing side, though, the bulk of that advanced equipment is at the leading-edge nodes. And while sales are expected to remain robust to deal with increasing volumes everywhere, the semiconductor industry seems to be looking more seriously at different approaches than just shrinking devices.

Materials are an important extension of that idea. Benedikt Ernst, head of business field semiconductor packaging solutions for Germany’s Merck, said progress is being made on directed self-assembly as an adjunct technology to EUV. Both rely heavily on new materials.

DSA has been gaining interest in advanced node scaling, as well, as a way of reducing line-edge roughness (LER). LER has always been an issue, but the problem is worse at 7nm and 5nm because the dimension of the patterns are starting to get close to the LER dimensions, said David Fried, chief technology officer at Coventor.

“You can actually get pattern healing through directed self-assembly,” said Fried. “There will also be deposition, etch and clean technologies that will work to heal pattern roughness in the patterning flow and the overall integration flow.”

Others are addressing LER using so-called smoothing techniques. This is done by smoothing out or fixing the rough edges or holes on patterns using ALE.

Fig. 2: Line edge roughness. Source: NIST

New structures and approaches
“The goal is to take the headroom that’s available and exploit it,” said , CEO of Teklatech. “We have to make designs easier to work with. We’re seeing more issues with timing and routability as power density goes up. Routability and power make it difficult to fix timing, and it’s worse at the most advanced nodes.”

This is one of the reasons there are so many new types of transistors on the drawing board at research houses such as Imec and Leti, as well as at TSMC, Intel Custom Foundry and Samsung Foundry. Among them are nanosheets and vertical and horizontal nanowires. So far, it’s uncertain which of those will be successful.

But chipmakers say that any future solutions now need to be thought about in more holistic terms. As new markets begin gaining steam, the entire semiconductor industry may require a reset, from initial concept and chip architecture all the way through to lithography, manufacturing tooling, materials and pre- and post-manufacturing validation and verification. The good news is that techniques developed at the most advanced nodes also can be used at older nodes, which helps reduce the cost and time it takes to achieve good yield.

Another option is to build chips with a number of different compute elements developed at different nodes. Intel and Samsung are leading the industry’s charge to the most advanced nodes, but they also have developed bridge technology for fan-out packages that are expected to include technology developed at multiple process nodes. All of the major foundries and packaging houses are working on this approach, as well, because it allows the most advanced nodes to be used for more regular logic structures that can be integrated with other components developed at older nodes.

“We’re seeing CoWoS (chip on wafer on substrate) being used for cloud servers, where you need more chips, more memory, and a silicon interposer for high performance and high bandwidth but not too much cost,” said Tom Quan, a director at TSMC. “And InFO (Integrated Fan-Out) has enough capability to satisfy anything in the mobile and IoT market. You can create a lot more derivatives and put them side by side or on top of each other, and you can add a couple of redistribution layers in a molding compound.”

Even there, new materials are being developed.

“There are a lot of research programs for resists and conductive paste, which is used pre-package to replace lead,” said Merck’s Ernst. “Some of these approaches use very thick resists, which are as large as 200 micrometers, to create copper pillars. DSA is making good progress, as well. There is continuing research, even though it is not yet commercialized. But right now there are no fundamental problems. At the same time, for existing nodes, we need very pure materials. You can shrink the structures, not the lithography, and that requires new materials on the front end and the back end.”

For the past couple of decades, and certainly since 45nm, most of the manufacturing side of the semiconductor industry has been obsessed with bringing EUV to market. Now that it is beginning to roll out, there is a collective sigh of relief that one of the most complex technologies ever invented appears to be working. While that will certainly help scaling to future nodes, market forces are pushing in many directions, not just down to smaller feature sizes.

For some, the key to scaling has always been about cost. For others, it has been about power and performance. Still, at the most advanced nodes, all three of those factors are becoming more difficult to achieve and alternatives approaches are becoming more popular. That doesn’t mean scaling is in jeopardy. But it does mean that it won’t work for everyone, and it may not be the only approach used even in devices where some of the smallest features sizes are deployed. Moore’s Law is alive and well, but it is no longer the only approach. And depending on the market or slice of a market, it may no longer be the best approach.

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Allen Rasafar says:

Great article on challenges of sub-10nm technology nodes. Despite some short-term good news it will be a long road to reaching viable productivity stage. Sub-10nm development has two phases that are overstated by foundries and confusing. First phase of development results, which are celebrated often as game changer, are coming from a controlled environment and not fully repeatable in a large scale production. The second challenge is mass production is const effectiveness that is reflected in Yield ramp-up. The good news about development in a controlled environment comes out first, but not so much gain is reached in mass production before hitting a yield ramp bottleneck curve. There are multiple challenges, from Patterning, Metrology, process tool and material calibration, to process control.The cost effectiveness is embedded in diligent process control methods that some Fabs are not implementing fast enough, as the traditional Fabrication BKM holds back the innovation that is urgently needed for success of the sub-10nm regime.

kthejoker says:

As someone with no background in semiconductor engineering, this article was fantastic, thank you.

memister says:

Obsession with EUV was indeed that. ASML had already given hints that EUV was not going to be single patterning.

No follow up on that?

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