Special Report
Pain Management
Second of two parts: Managing pain is literally a growing problem, extending from the block to the SoC to the software developer community and all the way into the cloud.
Top Stories
Architecting for Efficiency
To design an SoC most efficiently, there are many considerations to keep in mind.
Power Moves Up To First Place
At 28nm and beyond, the main technical hurdle to contend with is power. And no matter what tools or methodologies are thrown at it, it’s getting more difficult to manage.
Executive Insight: Simon Davidmann
The serial entrepreneur, investor and long-time industry insider sounds off on EDA, open source, and the importance of playing the cello.
The New Face of MCUs
New application areas that take advantage of more sophisticated microcontroller features equals expanded opportunities from the IoT to automotive and wearables to smartphones.
Blogs
Editor’s Note
Ed Sperling contends that The Denial Phase Is Over. Power considerations are no longer something to pass over with a nod. They’re an essential part of every design.
Power Awareness
Executive Editor Ann Steffora Mutschler looks at where are the most interesting IoT apps in Inspired By The IoT Yet? Hint: Anywhere and everywhere.
Power Aware A-Z
Mentor Graphics’ John Parry and Byron Blackmore uncork A High-Level ‘How To’ Guide For Effective Chip-Package Thermal Co-Design, seven important steps you need to build into your current and future flows deal with heat.
IP And LP In SoCs
Synopsys’ David Hsu argues in Rethinking Low Power Verification that for low power verification, it is not sufficient just to provide low-power checkers or to support low-power design intent.
Everything Low Power
Cadence’s Brian Fuller distills the key discussion points of a panel in Platforms, Standards, Methodologies Conquer Design Challenges. The good news is there are always ways through or around problems, no matter how daunting they seem at first.
Power Source
Ansys-Apache’s Aveek Sarkar finds that finFETs add challenges and increase existing ones, especially with power budgeting, voltage drop, EM and overall power-noise reliability sign-off in FinFET Based Designs: Power Analysis Considerations.
Jasper Gold
Joseph Hupcey examines the power consumed by low-power verification in User Case Study: Using Formal To Verify Low Power Functionality And Eliminate Unwanted ‘Xs.’
The Early Edition
Atrenta’s Mark Baker looks at current design methodologies and asks, Can RTL Power Estimation Accuracy Be Improved?
Power Down
Calypto’s Rob Eccles contends that the quality of switching activity information can have a direct effect on quality of results in Switching Activity And The Unknown.
At The Core
ARM’s Andrew Frame and Bee Hayes-Thakore take a look at the next phase of the IoT and find the market almost limitless in The Wearables Wave Expands Today’s Mobile Experience.
