Top Stories

Power Challenges At 10nm And Below
Dynamic power density and rising leakage power becoming more problematic at each new node.

Closing The Loop On Power Optimization
Minimizing power consumption for a given amount of work is a complex problem that spans many aspects of the design flow. How close can we get to achieving the optimum?

Analog’s Unfair Disadvantage
In a world that favors digital circuitry, analog has increasingly had to cope with processes that have become less favorable to them. But that may be changing.

Blogs

Editor In Chief Ed Sperling examines how quickly the switch to autonomous vehicles can occur, in The Future Of Sports Cars.

Executive Editor Ann Steffora Mutschler contends it is more important than ever to understand dynamic and leakage power and their place in the design flow, in Power Just One Piece Of The Puzzle At 10nm And Below.

Cadence’s Samer Hijazi pushes deeper into solving power limitations for convolutional neural networks on DSP processors, in part two of The Efficiency Problem.

Rambus’ Mohit Gupta finds Ethernet is moving faster than ever, presenting a distinct set of challenges for SerDes designers, in The SerDes-Terabit Ethernet Connection.

ARM’s Soshun Arai and Recognition Technologies’ Mark Sykes argue that making voice recognition work in the car requires the best of both local processing and the cloud, in Voice Recognition’s Role In Safer, More Secure Car Design.

Synopsys’ Ralph Grundler digs into adding flexibility to design by supporting multiple protocols in an interface system, in Building One Interface Subsystem For Multiple IoT SoCs.

Mentor’s Mike Santarini looks at why some EDA tools have kept the top spot for more than a decade, in Calibre Evolves Constantly.