Power Challenges At 10nm And Below

Dynamic power density and rising leakage power becoming more problematic at each new node.


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market.

Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as dynamic voltage and frequency scaling, body biasing, multiple power domains and dark silicon. Without these tricks, a chip would never be able to operate at 3 watts or less. However, keeping all of this under control is becoming more difficult with each new generation of finFETs.

Dark silicon essentially refers to the fact that we have too many functions crammed in a very small area,” said Jamil Kawa, a fellow in Synopsys’ Solutions Group. “Once you get to 16nm and below, you could literally put billions of devices on a chip, and therefore the amount of functions you could cram on a chip are tremendous.”

If all of those functions are turned on at the same time, a device will exceed the power and thermal budgets, causing a range of effects from thermally induced shutdown in a power-managed device, to self-heating and thermal runaway in one that doesn’t behave so predictably. At 7nm and 5nm, the problems are exacerbated for two reasons. First, dynamic current density increases because transistors are physically closer to each other in every direction, trapping heat between the fins. And second, below 16/14nm, current leakage begins increasing again, which also shows up as heat. In both cases, the effects need to be well understood because they can cause thermal and metal migration.

Fig. 1: What can go wrong. Source: Colbert Tech Repair/YouTube

“Self-heat is a problem and has to be modeled properly,” said Kawa. “This can be simulated using TCAD tools, and SPICE models that account for self-heat also can be created. You need to account for it in the degradation of the performance when you are characterizing your IP, and so on. Further, since copper is a soft metal, metal migration becomes a big problem. Therefore, metal migration analysis has to be exhaustive starting at 7nm.”

There are a number of solutions being proposed to deal with these problems. One involves a more aggressive application of the same concepts in use for the past few process nodes.

“The foundries are still achieving incredible progress and you can make a lot of transistors,” said Ashley Crawford, power architect and distinguished engineer at ARM. “If you put the two together, the less quoted ‘glass half full’ version of the dark-silicon thesis says you go toward using that area to implement efficient off-load accelerators, exploiting parallelism, to complement traditional design.”

Another twist on that idea utilizes what Stanford Professor William Dally terms “dim silicon.”

“The dim silicon concept says go ahead and continue operating everything you need to operate, but at a lower voltage,” Kawa said. “Since voltage contribution to power is a square ratio, you can still operate within your power budget at a much lower voltage, and much lower clock frequency, as opposed to being clever in architecture, which means the power management becomes an architectural problem. Still, the concept itself is very tricky.”

All of these solutions take advantage of a shift in thinking over the past few nodes, which is that power issues no longer can be solved at the block or even the subsystem level. They require a much more holistic approach.

“Whether the goal is to reduce on-chip power dissipation to reduce temperature, and minimize cooling requirements to reduce packaging cost, or to provide longer battery life, power is taking its place alongside timing as a critical dimension to be optimized during design,” said Sudhakar Jilla, group director of marketing for the IC implementation division at Mentor, a Siemens business.

In fact, power is now a key metrics for design closure. “Traditionally, power savings were mostly dependent on architectural level changes or clock gating schemes,” said Jilla. “But now designers are looking for smarter solutions that give more advantage in terms of power savings, especially at advanced nodes —16nm/14nm/10nm and below). FinFETs offer significant power savings compared to their planar counterparts. With multiple gates on either side of the conducting transistor ‘fin,’ there is much better control of the on/off characteristics of the gates. This comes at a cost of about three times higher input pin capacitance, but the much lower leakage power permits low supply. With finFETs, there has been a renewed focus on dynamic power minimization within the digital circuit design industry.”

What comes next?
Because of the investment in finFET processes and technology, chipmakers and foundries are trying to extend existing finFETs as long as possible. But as leakage begins increasing once again, there will likely be a shift to some new transistor device. The leading candidate today is the gate-all-around FETs, which will once again introduce new ways of dealing with power. A gate-all-around FET is basically a finFET turned on its side with a gate wrapped around it. How this ultimately behaves in real silicon is unknown, though, highlighting a need for much more system-level analysis.

“You have to start thinking about power integrity from a multi-physics perspective,” said Arvind Shanmugvel, director of application engineering at Ansys. “That includes timing, electromigration and thermal issues, and you have to make sure there is a complete chip-package-system solution. There is an impact on different types of physics if every timing path is impacted by voltage in different situations.”

Fig. 2: Self-heat modeling. Source: ANSYS

This holistic way of designing chips is getting much more traction these days, particularly when it comes to power. “Complexity is increasing in two dimensions,” said , CEO of Teklatech. “There are more complex designs and more physical dimensions. That requires a good analysis throughout the flow.”

Bjerregaard said there isn’t necessarily any one technical problem that needs to be addressed, but you do need to understand the effects of those problems. For instance, what impact does IR drop have on electromigration or aging? That can only be solved using a higher-level of abstraction to understand the multi-physics impact of design decisions. “You need to be able to filter out problems that don’t matter so you can fix the problem that does matter early.”

Unexpected problems
At every new node there are unexpected problems. In the past, those problems generally involved functionality and yield. But power-related issues increasingly are dominating designs, and those are often hard to predict because all of the data isn’t available at the same time.

Power issues are exacerbated by an explosion in the number of corner, mode, and power state scenarios that could have conflicting power, timing, system integration, manufacturability, and area closure requirements, said Mentor’s Jilla. “The basic low-power design techniques, such as clock gating for reducing dynamic power, or multiple voltage thresholds (multi-Vt) to decrease leakage current, are well-established and supported by existing tools for a single mode/corner combination. However, designers are running into difficulty with more advanced techniques, such as multi-voltage flows, designing for power in a multi-corner multi-mode context, and designing power-efficient clock trees. With a multi-voltage supply (also called multi-Vdd) approach, some blocks use lower supply voltages than others, creating voltage islands. This flow gets even more complex when dynamic voltage and frequency scaling is used to change the supply voltage level and clock frequency during operation.”

In designs with many corners and modes, clock power consumption depends on various factors such as the circuit design style, architectural choice, clock distribution wiring, clock driver sizing, and the capability to disable part of the clocking network using optimal clock gate placement.

Given all this, as power becomes one of the key limiting factors in IC design threatening the continuation of , engineering teams need new capabilities across the entire design flow that enable them to clearly see and understand the impact of power on their design. Arvind Naryanan, a product marketing manager at Mentor, suggested some of the key technologies now offered include:

  • Unified Power Format (UPF)-based RTL-to-GDSII flow, including support for power state tables;
  • Automated multi-voltage flow with support for dynamic voltage and frequency scaling (DVFS) to handle varying supply voltages and clock frequencies, and the capability to handle special cells such as level shifters, isolation cells, and multi-threshold CMOS (MTCMOS) power gates;
  • Power-aware clock tree synthesis with smart clock gate placement, slew shaping, register clumping, and concurrent MCMM optimization that ensures a balanced clock tree with the minimum number of clock buffers;
  • Power optimization throughout the implementation flow ensuring the best quality of results at advanced technology nodes with finFETs.

Dealing with resistance
The power profile of a chip has switched from being leakage dominated at 28nm to dynamic power dominated at 16/14nm, to a combination of both at 10nm, 7 nm, and 5.

“FinFET was a very elegant innovation because it allowed us to make smaller transistors that were a lot less leaky,” said Kam Kittrell, product management group director for the Digital & Signoff group at Cadence. “At the same time, the wires are getting closer together, the wires are getting taller in order to ameliorate the resistance impact, and the via cuts are getting more resistant. As a result, there is a lot more RC component in the wires for shorter distances.”

Also, the transistors that are driving the general-purpose transistors within the design are having to drive a lot more load in order to get to the destination, and there is a lot more dynamic power component.

“Looking back to 180nm designs, leakage was just becoming a problem, but dynamic dominated,” Kittrell said. “At that time the dynamic power could mainly be taken care of with I/Os, memories, and clocks. If you did something good in those areas, it was fine and you did what you could in order to get it under control. That’s changing, and the logic component (the data path logic and control logic) is becoming a pretty significant portion of the total dynamic power within the chip. So now we’ve got that component. It’s just managing the power, how much power is going in there, and also because of the effects, IR drop is becoming a bigger and bigger problem down toward the back end of the design.”

Solving these two big power problems of dynamic power and IR drop requires revisiting the entire flow, rather than looking to a single tool or methodology to solve all problems.

“What’s interesting about this is that it normally isn’t done for implementation, since it also has to take in verification components,” he said. “On dynamic power, whether you’re looking at the total power or some component of IR drop (either average IR drop or transient IR drop) you have to have vectors to stimulate those. If we look at the two ends of it, if I have dynamic power and IR drop at the beginning of the flow, I can have more impact on dynamic power than on toward the end. At both ends of the scale, there are also capacity issues so looking at total power at the beginning, if I am an RTL designer working one block, I may come up with a dynamic power that I think is fantastic but it turns out when I put it at the subsystem or the SoC level that my block is being exercised so little or so much that my view of the contribution to the total landscape is wrong. Because of this, you’ve got to have large capacity at the very beginning just in order to do verification of designs—speed at which you do simulation. Preferably you’re running system-level software to see what happens if the radio is being turned on or off, or listening to the music player or whatever it may be to see what the power profile is up front.”

ANSYS’ Shanmugvel agrees. “The underlying theme is that it is exponentially more difficult to close the signoff loop,” he said. “The only way to deal with this is for power integration to be looked at more from a big-data perspective.”

That also requires much more integration of tools so that a snapshot of power can be shared across the entire design flow every place it is needed. “There’s got to be a conduit kind of connecting technology that connects all of these power-aware [technologies] that also give indications very early on about power problems that could be popping up along the flow,” said Cadence’s Kittrell. “Right now, this is very ad hoc.”

—Ed Sperling contributed to this report.

Related Stories
Optimization Challenges For 10nm And 7nm (Part 1)
What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.
Optimization Challenges For 10nm And 7nm (Part 2)
Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotive that require robust, long-lived components.
Worst-Case Results Causing Problems
At 10nm and 7nm, overdesign can affect power, performance and time to market.


Kolio says:

“”transistors are physically closer to each other in every direction””
Gate pitch is much longer distance than diameter of transistor in nanometers.

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