tag: dark silicon

Striking A Balance On Efficiency, Performance, And Cost
By Ed Sperling - 11 Sep, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss power-related issues such as voltage droop, application-specific processing elements, the impact of physical effects in advanced packaging, and the benefits of backside power delivery, with Hans Yeager, senior principal engineer, architecture, at Tenstorrent; Joe Davis, senior director for Calibre interfaces and EM/IR product m... » read more

Balancing Power And Heat In Advanced Chip Designs
By Karen Heyman - 10 Nov, 2022 - Comments: 1

Power and heat use to be someone else's problem. That's no longer the case, and the issues are spreading as more designs migrate to more advanced process nodes and different types of advanced packaging. There are a number of reasons for this shift. To begin with, there are shrinking wire diameters, thinner dielectrics, and thinner substrates. The scaling of wires requires more energy to driv... » read more

Designing For Thermal
By Karen Heyman - 13 Sep, 2022 - Comments: 0

Heat has emerged as a major concern for semiconductors in every form factor, from digital watches to data centers, and it is becoming more of a problem at advanced nodes and in advanced packages where that heat is especially difficult to dissipate. Temperatures at the base of finFETs and GAA FETs can differ from those at the top of the transistor structures. They also can vary depending on h... » read more

More Options, Less Dark Silicon
By Ed Sperling - 20 Apr, 2022 - Comments: 0

Chipmakers are beginning to re-examine how much dark silicon should be used in a heterogenous system, where it works best, and what alternatives are available — a direct result of a slowdown in Moore's Law scaling and the increasing disaggregation of SoCs. The concept of dark silicon has been around for a couple decades, but it really began taking off with the introduction of the Internet ... » read more

DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors
By Technical Paper Link - 12 Apr, 2022 - Comments: 0

New research paper from ETH Zurich and others. Abstract "To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components' power supply using low-leakage transistors, called power-gates. Unfortunately, power-gates increase the system's power-delivery impedance and voltage guardband, limiting the system's maximum attainable voltage (i.e., ... » read more

Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance ... » read more

Where Timing And Voltage Intersect
By Ed Sperling - 14 Feb, 2020 - Comments: 0

João Geada, chief technologist at ANSYS, talks about the limitations for power delivery networks and what processors can handle, why the current solutions to these issues are causing failures, and how voltage reduction can affect timing. » read more

Thermal Challenges And Moore’s Law
By Ed Sperling - 22 Oct, 2019 - Comments: 0

Steven Woo, fellow and distinguished inventor at Rambus, looks at the evolution of graphics cards over a couple of decades and how designs changed to deal with more graphics and more heat, and why smaller, faster and cheaper doesn’t apply in this market. » read more

Low Power At The Edge
By Ed Sperling - 17 Jan, 2019 - Comments: 0

The tech world has come to the realization in recent months that there is far too much data to process everything in the cloud. Now it is starting to come to grips with what that really means for edge and near-edge computing. There still are no rules for where or how that data will be parsed, but there is a growing recognition that some level of pre-processing will be necessary, and that in tur... » read more

Custom Vs. Non-Custom Design
By Ed Sperling - 21 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss custom designs with Yong Pang, head of North American operations for [getentity id="22217" e_name="Imec"]; Phil Burr, director of portfolio product management for [getentity id="22186" e_name="Arm's"] embedded and automotive groups; Ambar Sarkar, chief technologist at eInfochips; and John Tinson, vice president of sales at Sondrel. What follows are ... » read more

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