Power Challenges At 10nm And Below

Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

The Power Game

By Ann Steffora Mutschler Semiconductor engineering teams always have focused on stepping up performance in new designs, but in the mobile, GPU and tablet markets they’re finding that maintaining the balance between higher performance and the same or lower power is increasingly onerous. The reason: Extreme gaming applications can create scenario files that cause dynamic power consumpt... » read more

Rounding Up Design Corners

By Pallab Chatterjee With advanced process development occupying the 32nm to 22nm corridor, production SoC and ASIC designs are being built at the 180nm to 45nm nodes. In these processes, the designer has to contend with cross-wafer variation and non-correlated design corners, as well as multiple operation states. This is referred to as multi-corner multi-mode (MCMM) and variation analysis. ... » read more