Rounding Up Design Corners

Multi-corner, multi-mode and variation analysis become critical even in chips that are not at the front edge of Moore’s Law.


By Pallab Chatterjee

With advanced process development occupying the 32nm to 22nm corridor, production SoC and ASIC designs are being built at the 180nm to 45nm nodes. In these processes, the designer has to contend with cross-wafer variation and non-correlated design corners, as well as multiple operation states. This is referred to as multi-corner multi-mode (MCMM) and variation analysis. And at the 45nm node, all of these analyses become mandatory.

To address the updated design flows for the 180 to 45nm process, static timing analysis (STA) is used to set up the system-level criteria for block-based IP that makes up the chip. This area has received updates on STA tools in the past few years to make them adaptable to the new processors and machines.

Mentor Graphics was one of the first to introduce a fully automated analytic solution with the inclusion of the MCMM capability that was part of the Olympus SoC Place and Route environment. This product was introduced supporting both distributed processing and multi-threaded/multi-core capabilities for handing large designs. Synopsys, around the same time as Mentor, introduced the VX extension to its industry “gold-standard product” Prime Time. The product likewise was introduced supporting multi-core/multi-threading and distributed processing for faster throughput. Both of those products maintain their accuracy while significantly updating performance and automation. The tools are utilizing a licensing model that is different from the standard one, so the MCMM analysis does not require a license for each corner simulated.

To address the needs of the new processes, there are number of multithreaded single-machine, single-license STA tools on the market that replace the function of distributed processing of multiple simulations, one for each corner or mode, on a different machine requiring a separate license. The capabilities of these new tools are targeted at embedded controller and embedded processor applications that have a very large state space. These tools, from Mentor, Synopsys and, now, Magma, automatically perform static timing analysis over the full design space and dump the results into their respective databases, without the new user starting the runs for the individual corners and correlating the results.

Device-level simulation has changed and now requires them to be multi-threaded and multi-core aware. HSPICE, Eldo, Spectre, and SMARTSPICE have been on the market for several years and have recently been joined by the FineSim simulator from Magma. These tools identify the corners of the MCMM space and then perform a reduced number of simulations to cover the space based on algorithmic determination of what are relevant points in the design space, rather than traditional Monte Carlo variation analysis. The reduced space is more representative of the realizable corners in the process, and produces results, of the same accuracy, significantly quicker.

Other simulators supporting a reduced design space simulation environment include HSPICE and SMARTSPICE. Solido Design Automation has variation analysis engine that supports Spectre and the Berkeley Design Automation Simulators for the reduced state space analysis. The Solido tool is built around a visualization environment that not only drives the simulations for a reduced simulation space, but uses active trend identification to help steer the design toward a targeted specification.

All the main players in EDA now have tools to address the automated design verification of MCMM design applications. The new process technologies no longer have simple correlated design corners (fast, nominal, slow). Instead, they have uncorrelated device model properties with global process and cross-wafer variation. In order to signoff on designs in these processes, (65nm and below), Monte Carlo or advanced variation analysis are the only methods to understand the design.

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