Power Challenges At 10nm And Below


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

IC Validator Programmable EERC Mixed Mode Checking Technology


Traditional visual inspection or manual checking for electrical rule compliance is both time consuming and error prone. A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper is a companion to the introductory IC Validator programmable Extended Electrical Rule Check (EERC) white paper on netlist domain che... » read more