Tech Talk: 5/3nm Parasitics

What to expect at future process nodes.

February 22nd, 2018 - By: Ed Sperling

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs.

Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

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Tech Talk: 5/3nm Parasitics

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Tech Talk: 5/3nm Parasitics

Ed Sperling

Leave a Reply Cancel reply

Knowledge Centers Blogs

Multiple Patterning

Double Patterning

Cell-Aware Test

Process Variation

Technical Papers

Trending Articles

Using Memory Differently To Boost Speed

HBM2E: The E Stands for Evolutionary

Week In Review: Manufacturing, Test

Cloudy Outlook Seen For IC Biz

Hardware-Software Co-Design Reappears

Knowledge Centers Entities, people and technologies explored

Related Articles

The Case For Embedded FPGAs Strengthens And Widens

Will Open-Source EDA Work?

Open Source Processors: Fact Or Fiction?

How To Integrate An Embedded FPGA

Hardware-Software Co-Design Reappears

Automotive, AI Drive Big Changes In Test

Training Tomorrow’s Chip Designers

CEO Outlook: It Gets Much Harder From Here

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