What to expect at future process nodes.
Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs.
DARPA and a number of major vendors are backing this modular approach, but hurdles remain.
Using the Von Neumann architecture for artificial intelligence applications is inefficient. What will replace it?
D2S’ CEO sounds off on the impact of deep learning, EUV and other manufacturing advancements.
It’s been an uneven path leading to the current state of AI, and there’s still a lot of work ahead.
Shift to cloud model has kept power consumption in check, but that benefit may have run its course.
Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.
What AI and deep learning are good for, what they’re not good for, and why accuracy sometimes works against these systems.
What happens when companies are combined? The outcome often isn’t as good as the announcement.
Acceleration of advanced processes, skyrocketing complexity and cost, and concerns about IP availability are raising some difficult questions.
As complexity and device sizes rise, so does the need for an on-chip network.
Part 1: New opportunities and potential pitfalls in automotive, 5G, connected intelligence and infrastructure as a service in EDA.
Experts at the Table, part 1: While the Cloud may be ready for EDA, it is not clear how ready EDA is for the Cloud. What needs to change?
Synopsys Co-CEO Aart de Geus explains why systemic complexity will be the next big challenge, and what that means for EDA and the chip industry.
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