Tech Talk: 5/3nm Parasitics
What to expect at future process nodes.
February 22nd, 2018 -
By:
Ed Sperling
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Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs.
VIDEO
Ed Sperling (all posts)
Ed Sperling is the editor in chief of Semiconductor Engineering.
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