What to expect at future process nodes.
Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs.
Comment
Name * (Note: This name will be displayed publicly)
Email * (Note: This will not be displayed publicly)
Save my name and email in this browser for the next time I comment.
Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.
Costs of developing a complex chip could run as high as $1.5B, while power/performance benefits are likely to decrease.
Experts at the Table, part 1: Why machine learning works in some cases and not in others.
What AI and deep learning are good for, what they’re not good for, and why accuracy sometimes works against these systems.
Continued integration is no longer the natural way forward for semiconductors. What needs to happen to make it easier?
Goal is to improve quality while reducing time to revenue, but it’s not always so clear-cut.
But working with this architecture has some not-so-obvious pitfalls, and new tools licensing options may be necessary.
So far there are no tools and no clear methodology to eliminating bugs. That would require understanding what an AI bug actually is.
When does a large amount of data become Big Data, and could system-level verification benefit from it?
Acceleration of advanced processes, skyrocketing complexity and cost, and concerns about IP availability are raising some difficult questions.
Part 1: New opportunities and potential pitfalls in automotive, 5G, connected intelligence and infrastructure as a service in EDA.
Email:
Interests: System-Level Design Low Power-High Performance Manufacturing & Process Tech Packaging, Test & Materials IoT, Security & Automotive
Leave a Reply