What to expect at future process nodes.
Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs.
Array
(
[0] => 24100196
[1] => 24100197
[3] => 24100245
[5] => 24100247
[7] => 24100174
)
The promise of advanced packaging is being able to integrate heterogeneous chips, but a lot of work is needed to make that happen.
Improvement still needed for uptime, defectivity, line edge roughness and process flows.
Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Researchers digging into ways around the von Neumann bottleneck.
Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.
Optimizing complex chips requires decisions about overall system architecture, and memory is a key variable.
Why data scrubbing and social issues could limit the speed of adoption and the usefulness of this technology.
Wally Rhines, Mentor’s CEO Emeritus, points to big shifts caused by AI, customization, uncertainty in the global economy and a changing customer base.
Smaller features and AI are creating system-level issues, but traditional ways of solving these problems don’t always work.
Agile development is gaining traction for developing hardware testbenches, but challenges remain.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply