What to expect at future process nodes.
Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs.
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30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
Leaders of three R&D organizations, Imec, Leti and SRC, discuss the latest chip trends in AI, packaging and quantum computing.
Applied Materials’ VP looks at what’s next for semiconductor manufacturing and the impact of variation, new materials and different architectures.
What could make this memory type stand out from the next-gen memory crowd.
Researchers digging into ways around the von Neumann bottleneck.
Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.
This will go down as a good year for the semiconductor industry, where new markets and innovation were both necessary and rewarded.
The term creates hope for some, fear for others, and confusion for all.
Researchers digging into ways around the von Neumann bottleneck.
Optimizing processor architectures requires a broader understanding data flow, latency, power and performance.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
Optimizing complex chips requires decisions about overall system architecture, and memory is a key variable.
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