Tech Talk: 5/3nm Parasitics

By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

Changing Direction In Chip Design

By Ed Sperling - 26 Jan, 2017 - Comments: 1

Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

What Works After 7nm?

By Mark LaPedus - 20 Aug, 2015 - Comments: 3

An Steegen, senior vice president of process technology at [getentity id="22217" e_name="Imec"], the Belgium-based R&D organization, sat down with Semiconductor Engineering to discuss the future of process technology and transistor trends all the way to 3nm. SE: Some say the semiconductor industry is maturing. Yet we have more device types and options than ever before, right? Steegen:... » read more

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tag: vertical nanowire FETs

Tech Talk: 5/3nm Parasitics

Changing Direction In Chip Design

What Works After 7nm?