Special Report
Is DVFS Worth The Effort?
Dynamic voltage and frequency scaling can save a lot of power and energy, but design costs can be high and verification difficult.
Top Stories
Dealing With Device Aging At Advanced Nodes
Gaps remain, but understanding about how circuits age and what to do about it is improving.
Compiling And Optimizing Neural Nets
Inferencing with lower power and improved performance.
Blogs
Fraunhofer EAS’ Benjamin Prautsch examines the tension between creative, precise high-end layouts and firmly established tapeout deadlines, in Analog Chip Layout: Creativity Vs. Deadlines.
Synopsys’ Ron Lowman looks at the factors driving the development of edge computing and the benefits it could provide to a network, in AI & IP In Edge Computing For Faster 5G And The IoT.
Rambus’ Vinitha Seevaratnam explains why rapidly rising data traffic and ever-greater bandwidth requirements are driving the need for new interfaces in the data center, in PCIe 5.0: A Key Interface Solution For The Evolving Data Center.
Mentor’s Akshay Sarup steps us through how to speed up the PCIe link training and initialization process, plus creating custom testbenches that can dynamically adapt to different IP topologies and configurations, in Accelerating Simulation Of PCIe Controllers For DMA Applications.
Arm’s Pierre-Alexandre Bou-Ach sees great potential to achieve better energy efficiency later in the IC development flow, in Optimizing For Energy In Physical Design.
Moortec’s Lee Vick recounts how a gun made in a dungeon changed the world and how it relates to chip manufacturing, in A Historical Case For Precision.
Cadence’s Paul McLellan previews what’s new and upcoming from TSMC, including for automotive and advanced packaging, in OIP Ecosystem Forum 2020.
Ansys’ Marc Swinnen points out that the world’s leading chip designers feature at the upcoming IDEAS Digital Forum show, in Learn How To Streamline Design Flows And Reduce Design Cost.
