Top Stories

Enabling Cheaper Design
At what point does cheaper design enable a significant growth in custom semiconductor content? Not everyone is onboard with the idea.

Process Corner Explosion
At 7nm and below, modeling what will actually show up in silicon is a lot more complicated.

Minimizing Chip Aging Effects
Understanding aging factors within a design can help reduce the likelihood of product failures.

Video

Hybrid Memory
Tech Talk: How long can DRAM scalIng continue?

Blogs

Editor In Chief Ed Sperling contends that just building systems based on speed now comes with a well-publicized risk, in The Security Penalty.

Mentor’s Progyna Khondkar finds that low power coverage remains a missing piece of the functional verification environment, in Solving Puzzling Power-Aware Coverage: Getting An Aggregated Coverage Metric.

Cadence’s Marc Swinnen observes that at the latest nodes, it is becoming impossible to analyze IR drop correctly, in Designers Face Growing Problems With On-Chip Power Distribution.

Fraunhofer’s Jens Michael Warmuth examines the current state and future development of a key concept for reliability assessment, in Mission Profiles.

Moortec’s Ramsay Allen argues that from identifying hot spots to individualizing optimization schemes, it’s important to know what’s going on inside a chip, in 5 Reasons Why In-Chip Monitoring Is Here To Stay.

Synopsys’ Dana Neustadter looks at where security is needed in AI environments, in Is Your AI SoC Secure?

Arm’s Brian Fuller zeroes in on the growing focus on functional safety in autonomous and semi-autonomous vehicles, in Open Throttle On Automotive Innovation.