Top Stories

Making Chips Run Faster
Just turning up the clock frequency or using more cores will drain the battery or cook the chip, but there are lots of other options.

Limiters To The Internet Of Things
There are several factors limiting adoption of the Internet of Things, but industrial applications are likely to be the long term drivers.

Design For IoT
Will the Internet of Things drive development of new power-aware design techniques? You can bet on it.

Are We Headed For A Power Wall?
Predictions of doom may be overstated, but there are challenges looming in power reduction.

IoT Brings Low Power To Forefront
Low power design requirements for the Internet of Things may drive EDA products into different directions.

Blogs

Editor in Chief Ed Sperling contends that Apple’s announcements this week are less about the devices than the back-end system that supports them in Apple Legitimizes The IoT.

Executive Editor Ann Mutschler observes that while a lot of attention is showered on power reduction for handhelds and IoT apps, concerns are much different on the other side in Datacenter Power Is Different.

Cadence’s Brian Fuller argues that we need a visionary to offer glimpses into what technology can become, not just modifications of what is already here, in Where Is Gene Roddenberry When You Need Him?

ARM’s Leah Schuth digs deep into design-specific solutions to increase PPA and cut time to market in How To Reduce Implementation Headaches In FinFET Processes.

Synopsys’ Navraj Nandra finds much already available to reduce a design’s overall power consumption in Advances in Power Management For Physical IP In 28nm And FinFET Process Nodes.

Mentor Graphics’ Jim Kenney writes that EDA vendors need to provide designers with an option to trade off power estimation granularity with processing time during different phases of development in Extending Power Analysis To The Emulation Of Complex SoCs.

Ansys-Apache’s Preeti Gupta questions whether RTL power can adequately model key physical aspects of clocks to make reliable power-related decisions, and what complexities are added after 20nm in Can RTL Clock Power Be Accurate Enough For Sub-20nm Multi-GHz Designs?

Calypto’s Anand Iyer digs into why it is so important to do analysis at the RTL in Low Power Design: RTL Power Analysis.

Atrenta’s Kiran Vittal observes how important it is to secure Manufacturing Test Robustness at the RTL.

Rambus’ Joe Gullo notes that the pace, cost and complexity of scaling makes it impossible to proceed without partners in Collaboration Accelerates Moore’s Law.