How To Reduce Implementation Headaches In FinFET Processes

In this era of compressed market windows and shrinking or changing technology, today’s engineers are always looking for ways to improve their overall product performance, power and area (PPA), while also decreasing their SoC design effort. The goal is to ease time-consuming and labor-intensive implementation tasks that will yield a reduction in design time, without sacrificing accuracy and optimization capability is the key to success.

Inherent finFET power grid and signoff design challenges
Using traditional place and route tool power grid commands will not create optimal power grids for the architecture of the ARM Logic Products. This is a problem. Designers must be able to optimize the power grid seamlessly with the physical IP in order to provide the best power, performance and area. It also would be great if the whole process was so easy that it was transparent to the user. Now that really would save time.

Let’s consider a methodology that would be especially useful for finFET and double-patterned designs—for example, an efficient process that would address challenges such as half-track libraries, pitch misalignment, complex design rules, and boundary cell requirements. Automating these critical aspects of floor planning with the interactive capability to build an optimal power network would help to improve overall power, performance and area. This would eliminate the need for implementation teams to study and apply detailed finFET design rules, allowing time to explore the right balance of design-specific power network options. It would improve design density, prevent pin access problems, and also correct rail sizing and offsets to avoid DRC violations. In addition, it would help prevent performance issues due to insufficient power networks and enable the best usage of power gating and power management cells.

Power Network with Power Gating Example

We also should explore the issue of on-chip variation, especially concerning for new stage-based OCV signoff foundry recommendations. Both voltage (~51%) and process (~48%) variations are equally guilty sources of random variation, with temperature variation trailing behind at about 1%. Typical stage-based OCV has its limitations, including the fact that the format does not account for load and slew, so the models may not provide precise data for timing closure. The delay variation, or derate factor, versus load/slew past a certain point may be underestimated.

On-chip Variation Example
Designers will require increased accuracy for their designs using the new SB-OCV foundry signoff recommendations. This includes having access to more precise data than currently is available with SB-OCV derate tables. Using expanded derate values outside of the SB-OCV characterization range to provide more exact derating — and reassigning these values to outlying instances — will become critical to delivering a confident signoff scenario. In addition to statistical constraint margining, flop hold constraint variation is also a foundry requirement. This variation is included within characterization tables to avoid the alternate requirement of adding a flat derate value, which can degrade overall PPA.

The goal: easing implementation
Having a methodology to automate power grid design and improve overall power, performance and area, in addition to adding more accurate data and precision to a signoff process that will also meet new foundry recommendations for FinFET process, is going to be crucial for successful future tapeouts. The ability to ease implementation headaches with design-specific solutions for advanced process designs will mean less worry for designers and more design success.