Inevitable Bugs


Are bug escapes inevitable? That was the fundamental question that Oski Technology recently put to a group of industry experts. The participants are primarily simulation experts who, in many cases, help direct the verification directions for some of the largest systems companies. In order to promote free discussion, all comments have been anonymized, distilling the primary thoughts of the parti... » read more

Redefining Device Failures


Can a 5nm or 3nm chip really perform to spec over a couple decades? The answer is yes, but not using traditional approaches for designing, manufacturing or testing those chips. At the next few process nodes, all the workarounds and solutions that have been developed since 45nm don't necessarily apply. In the early finFET processes, for example, the new transistor structure provided a huge im... » read more

Speeding Up Verification Using SystemC


Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Abstract Verification


Verification relies on a separation of concerns. Otherwise the task has no end. Sometimes we do it without thinking, but as an industry, we have never managed to fully define it such that it can become an accepted and trusted methodology. This becomes particularly true when we bring abstraction into the picture. A virtual prototype is meant to be true to behavior, but there could be timing d... » read more

IP Management And Development At 5/3nm


The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

Seeing Is Believing: Visualizing Full Coverage Closure In Low-Power Designs


By Madhur Bhargava and Durgesh Prasad Lowering the power consumption and leakage in SoCs and other electrical designs has become a paramount concern in recent years. The reasons for this are many and well understood. The structures and techniques we use to accomplish this have made verification of so called low-power designs more complex and difficult than it is for designs where power usage... » read more

The Single Best DFT Move You Can Make


A proven method to simplify a complex problem is to break it into smaller chunks. In the case of today’s large, complex SoCs, this means using hierarchical methods to design the blocks, then combine the results at the top level. While this sounds obvious, it hasn’t always been practical or technologically feasible to perform some tasks, like DFT, at the block level and translate that work s... » read more

Boosting Analog Reliability


Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

Boosting Regression Throughput By Reusing Setup Phase Simulation


This paper discusses how to write a design so the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. It also discusses what type of designs are appropriate for this methodology and what a designer can do to make his/her design suitable for it. Also c... » read more

Tech Talk: 7nm Process Variation


Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

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