tag: methodology

STMicroelectronics Methodology And Process For Heterogeneous Automotive Package Design
By Siemens EDA - 06 Oct, 2021 - Comments: 0

As a leading supplier of automotive semiconductors, STMicroelectronics must continue to move fast to develop and deliver leading-edge solutions. Employing package design as part of system innovation requires the STMicroelectronics Back-End Manufacturing Technology R&D organization to embrace the key driving forces of product development. In the automotive field, package designers need to... » read more

Getting Realistic About AI
By Olaf Enge-Rosenblatt - 12 Jul, 2021 - Comments: 0

By Olaf Enge-Rosenblatt and Andy Heinig The topic of artificial intelligence (AI) is omnipresent today, both in the news and on popular science shows. The number of possibilities for AI methods to assist people in making decisions are expanding rapidly. There are three main reasons for this: The development of new AI methods (deep learning, reinforcement learning); The continuous ... » read more

Clarifying Language/Methodology Confusion
By Aldec - 28 Oct, 2020 - Comments: 0

Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only add to the confusion. This document tries to clarify the situation. Click here to read more. » read more

Searching For Power Bugs
By Brian Bailey - 15 Oct, 2020 - Comments: 0

How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

Universal Verification Methodology Running Out Of Steam
By Ann Mutschler - 30 Jul, 2020 - Comments: 2

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more complex, and significantly larger, UVM is running out of steam. Consensus is building that some fundamental changes are required, moving tools up a level of abstraction and making them more ag... » read more

Inevitable Bugs
By Brian Bailey - 29 Apr, 2020 - Comments: 3

Are bug escapes inevitable? That was the fundamental question that Oski Technology recently put to a group of industry experts. The participants are primarily simulation experts who, in many cases, help direct the verification directions for some of the largest systems companies. In order to promote free discussion, all comments have been anonymized, distilling the primary thoughts of the parti... » read more

Redefining Device Failures
By Ed Sperling - 07 Apr, 2020 - Comments: 0

Can a 5nm or 3nm chip really perform to spec over a couple decades? The answer is yes, but not using traditional approaches for designing, manufacturing or testing those chips. At the next few process nodes, all the workarounds and solutions that have been developed since 45nm don't necessarily apply. In the early finFET processes, for example, the new transistor structure provided a huge im... » read more

Speeding Up Verification Using SystemC
By Ed Sperling - 23 Mar, 2020 - Comments: 0

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Abstract Verification
By Brian Bailey - 24 Oct, 2019 - Comments: 1

Verification relies on a separation of concerns. Otherwise the task has no end. Sometimes we do it without thinking, but as an industry, we have never managed to fully define it such that it can become an accepted and trusted methodology. This becomes particularly true when we bring abstraction into the picture. A virtual prototype is meant to be true to behavior, but there could be timing d... » read more

IP Management And Development At 5/3nm
By Ann Mutschler - 24 Oct, 2019 - Comments: 1

The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

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