Special Report

Power Delivery Affecting Performance At 7nm
Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.

Top Stories

Power Issues Grow For Cloud Chips
Optimizing processor design in high-performance computing now requires lots of small changes.

Reliability, Machine Learning And Advanced Packaging
Experts at the Table, part 1: The biggest concerns in chip design and how new markets and technologies are affecting them.

Blogs

Editor In Chief Ed Sperling contends that inferencing is the next battleground, in Making AI Run Faster.

Executive Editor Ann Steffora Mutschler observes that engineering teams are starting to make SoC design choices based on manufacturing effects, in ML Becomes Useful For Variation Coverage.

Mentor’s Rohit Jain zeroes in on a new reuse methodology that shortens drawn-out design verification cycles, in Re-Using Common Simulation Set-Up Processes To Speed Regression.

Synopsys’ Himanshu Bhatt digs into a low power methodology that uses a combination of static and dynamic verification, in Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs.

Fraunhofer’s Roland Jancke looks at using an integrated model-based flow for more efficient safety-aware design, in Functional Safety And Requirements Engineering.

Rambus’ Mondeep Thiara argues that automotive chipmakers face requirements not found in other consumer electronics, in ADAS Further Extends 7nm Challenges.

Cadence’s Lazaar Louis finds the move away from general-purpose CPUs is driving architectural innovation, in Processors Are Exciting Again.