ML Becomes Useful For Variation Coverage

Engineering teams are starting to make SoC design choices based on manufacturing effects.


According to industry sources, it is quite a feat to get a chip back from the foundry that actually meets the specifications the design team worked towards, and because of this much effort is underway across the industry to understand what will happen to a design once it reaches the manufacturing stage, and what the effects of design choices actually are.

AI and ML are absolutely the buzz words du jour, but it is encouraging to see that real technologies are emerging in an effort to push the envelope for designers, as Jeff Dyck, director of engineering at Mentor, a Siemens Business, explained. “Machine learning methods can increase coverage of variation effects by orders of magnitude without increasing schedule. This enables designers to substantially tighten margins, unlocking big wins for performance and power.”

For example, Solido (now Mentor) Variation Designer uses adaptive machine learning methods to deliver full coverage of the variation space orders of magnitude faster than brute force methods, which provides full verification within production schedules, Dyck said.

He said much of Solido’s technology works by running a design of experiments, building regressors and classifiers, predicting performances of the entire space, then adaptively zeroing in on areas of interest and areas of greatest uncertainty. Most of the variation space is covered using machine learning models, which deliver results almost instantaneously, while the most important areas are automatically simulated in SPICE for perfect accuracy. Designers use this coverage and precision to much more aggressively margin their circuits, improving performance, power, and area.

Further, Dyck said, many of the top 20 semiconductor companies have already adopted machine learning methods in production for the purpose of accurately and comprehensively measure variation effects and to tighten margins. He believes machine learning for variation is quickly becoming the new normal for transistor-level variation-aware design, and the next generation of CPUs will perform better and use less power as a result.

And this is just one example.

At the same time, along with applying machine learning techniques to existing tools, EDA tool providers are continually improving existing algorithms in tools, or even revamping them from the ground up. Tighter integrations between tool areas is also occurring in order to improve design tool efficiency, and bring increased knowledge from the design flow to the designer.

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