Top Stories
Design For Advanced Packaging
Stacking die is garnering more attention, but design flows aren’t fully ready to support it.
Taming NBTI To Improve Device Reliability
Negative-bias temperature instability can cause an array of problems at advanced nodes and reduced voltages.
Computing Way Outside The Box
Arm’s CTO talks about how AI and the end of Moore’s Law are shaking up processor design.
Blogs
Editor In Chief Ed Sperling points to a massive amount of hardware and software engineering that will be required to handle an explosion in data, in Accelerators Everywhere. Now What?
Executive Editor Ann Steffora Mutschler finds progress in the ability of EDA tools and IP to address transistor aging, in Aging Analysis Hits Mainstream.
Mentor’s John Ferguson examines the key innovations that made pure-play foundries and the fabless revolution possible, in The Process Design Kit: Protecting Design Know-How.
Fraunhofer’s Andy Heinig contends there is no easy to solution for conflicting goals that make arranging copper pillars or microbumps around hard IP difficult, in Interaction Of Hard IP And Chip-Package.
Synopsys’ Rita Horner looks at the new 400 Gb/s Ethernet standard, which provides a range of interfaces for varying length and throughput requirements, in Next-Generation Ethernet Interconnects For 400G Hyperscale Data Centers.
Cadence’s Ronak Shah digs into 5G and why power consumption remains a major barrier, in Psst, Says 5G…Wanna See What My New Antenna Tech Challenge Looks Like?
