Top Stories

Re-Architecting SerDes
As implementations evolve to stay relevant, a new technology threatens to overtake SerDes.

Low Power Still Leads, But Energy Emerges As Future Focus
More data, more processors, and reduced scaling benefits force chipmakers to innovate.

Waking And Sleeping Create Current Transients
How to keep power down, performance up, and lower peak currents.

Blogs

Mentor’s Russell Klein identifies significant contributors to performance and efficiency for custom developed hardware inferencing accelerators, in Fast, Low-Power Inferencing.

Synopsys’ Vadhiraj Sankaranarayanan explains how side-band, inline, on-die, and link error correcting schemes work and the applications to which they are best suited, in What Designers Need To Know About Error Correction Code (ECC) In DDR Memories.

Fraunhofer’s Jens Michael Warmuth contends that rethinking of classic concepts is required for autonomous vehicles to be affordable, in Functional Safety For Fail-Operational Systems.

Cadence’s Paul McLellan looks at how to make photonics chips compatible with existing OSAT assembly and test lines, in Attaching Fibers To Photonic Chips.

Arm’s Dylan Zika warns that a lack of a common understanding of performance is hampering AI growth, in Standard Benchmarks For AI Innovation.

Rambus’ Joseph Rodriguez goes under the hood of an HBM2E memory interface with enough bandwidth for AI and HPC applications, in Pushing The Envelope With HBM2E Memory.

ANSYS’ Susan Coleman shows how a Spanish startup is taking on designing the ground transportation system of the future, in Simulating The Hyperloop.