Attaching Fibers To Photonic Chips

Making photonics chips compatible with existing OSAT assembly and test lines.


Recently, Cadence held its fifth photonics summit, CadenceCONNECT: Photonics Contribution to High-Performance Computing. You can read my earlier posts:

The third day was all about how to connect the incoming and outgoing fibers to the photonics chips. I will cover more details below, but there are three basic approaches:

  • Active, and powered up: The chip is powered up (in a test mode), the fiber is aligned with the chip, and the chip gives feedback as to how perfect the optical connection is so that the connection can be adjusted.
  • Active, but not powered up: The fiber is aligned with the chip but it is not powered up. But there are waveguides on the chip that allow the quality of the alignment to be measured externally even so since waveguides transmit light even if not powered up.
  • Passive: The assembly process assembles the fiber and the chip in a way that does not depend on feedback about how much light is getting through.

In the Q&A, which I moderated, this was one of the big discussions. The tradeoffs seemed to be that for high volume, passive alignment is much cheaper. For the absolute best alignment with the absolute lowest light loss, active cannot be beaten.

Another issue is making the approach as compatible as possible with existing OSAT assembly and test lines. It is obviously very expensive to build a special production line, rather than add a few steps (or even none in one presentation) to an existing production flow. After all, one of the big advantages of silicon photonics is that it leverages existing 300mm silicon foundry production lines and adds a few steps. We need to do the same for connecting the fibers.

Yet another issue is that whatever we do has to be able to cope with solder reflow, both during assembly at the package level, and also during PCB assembly. That makes the choice of materials important (since they can’t melt at too low a temperature). We face a similar limitation in IC fabrication since interconnect metal cannot survive at the temperatures in the diffusion furnaces.

However, it is inevitably more complex and expensive to do all the normal assembly stuff (after all, there are still electronics on all these chips) and also add these additional steps. In fact, whereas building a normal (non-photonic) chip, the fabrication is the bulk of the cost and assembly and test is perhaps 20%, while for silicon photonics it is the other way around. Building the chip is cheap, but the cost of the package and the additional steps required for assembly and test make up about 80% of the cost.

The speakers were:

  • Alexander Janta-Polczynski of IBM: “Efficient Assembly and Packaging for Photonics” (in the passive camp)
  • Lukas Chrostowski of University of British Columbia: “Photonic Wirebonds for Silicon Photonics: Early Results from SiEPICfab” (passive, but in a camp all of his own)
  • Ed White of AIM: “Rochester Test Assembly Packaging Facility for Photonics Systems – Research Project Update” (active)
  • Hersham Taha of TeraMount: “Foundations for Scalability of Chip-to-Chip Connectivity” (passive)


I’ve actually written about the basic process that IBM uses before, in my 2017 post GF Silicon Photonics: Fiber Attach Is the Secret Sauce.

Alexander is a Professional Engineer at their test and assembly operation at Bromont (a suburb of Montréal). IBM calls its main assembly technique “fiber in V-groove.” This has passive self-alignment (so no analysis of light paths during assembly) and high throughput.

Basically, V-shaped grooves are etched into the die, the fibers are put in a jig and pressed into the grooves. If the fibers are slightly misaligned, the shape of the grooves will align them as they are pressed down. They are glued in place with a glue that is cured by UV-light in just five seconds.

The above diagram shows the process in a bit more detail, and on the right how the self-alignment actually works. They have done assemblies with 12 fibers, and are working on 16 now.


The heart of Lukas’s presentation is what he calls “photonic wirebonding”. The process is pretty amazing, a cross between chip wirebonding, 3D printing, and lithography. Here’s how it works.

The chips and the fiber(s) are put on a carrier. High-resolution imaging is then used to calculate exactly where the connection sites are, in much the same way as a wafer-stepper aligns precisely. The whole thing is then coated with a special photoresist. This is then structured in three dimensions with a laser. The resist changes to an optically transparent and rigid “wire.” Finally, the resist is stripped off leaving just the wires.

These are fragile and so finally a protective layer is added to prevent physical damage.

Above is a photo of a real system. To the top is a normal chip, wirebonded to the silicon photonic chip (blue). To the left are InP lasers (pink). To the right are the outgoing fibers. All the connections from the lasers and to the fibers are done using photonic wire bonds.


Ed described the capabilities of AIM’s Rochester Test and Packaging facility (TAP). Most of what he discussed was microelectronic assembly. But for this blog post, this was his description of their capabilities in photonics. Note that all the photonic assembly is active, and requires the devices to be powered up or have appropriate optical loopback.


Hesham had another passive assembly approach. He started out by pointing out that what made microelectronic packaging successful was the hierarchy of platforms and connectors. The important thing is that (not counting wirebonding) when one platform is put on top of another, all connections are made simultaneously. His goal is to do the same with optical connectivity using what he calls “photonic bumps.”

This is an example. The pink lines are waveguides. The little squares are the photonic bumps. Underneath (out of sight) are bumps to connect the electronics in the usual way when this platform is put on top of the lower one. The idea is to connect optics and electronics by a single chip placement.

This is a microscope photo of a couple of waveguides terminated with 3D structures manufactured at the wafer level. Inside are turning mirrors and lensed mirrors.

Above are the pros and cons of this approach. Basically, it makes optical assembly almost completely like electrical assembly and done at the same time.

This doesn’t directly cover the fiber attach. This is done with the “photonic plug” attached to the photonic bump. The fiber insertion has “self-aligning optics”, as in the diagram below.


This was a fascinating morning, with four very different approaches to connecting the fibers to the chips:

  • IBM’s V-groove self-aligned insertion in high-volume production
  • UBC’s photonic wirebond, in development
  • AIM’s active fiber-attach, in medium-volume production
  • TeraMount’s photonic bumps, in development

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