Top Stories
DRAM’s Whac‑A‑Mole Security Crisis
New refresh commands chase Rowhammer and Rowpress, but a permanent fix remains years away.
A New Era For Co-Processing
Processor architectures are evolving faster than ever, but they still lag the pace of AI development. Chip architects must predict what will be required tomorrow in today’s designs.
Fast Isn’t Fast Enough: Redefining Metrics For Edge AI
Why latency guarantees, memory movement, power budgets, and rapid model deployment matter more than raw TOPS.
Video
State Of The Market For Edge Silicon
What makes one AI chip better than another?
Memory For AI At The Edge
Why new LPDDR releases make them the memories of choice for many applications.
Sponsor Blogs
Rambus’ Lou Ternullo finds that careful coordination between the PHY and controller layers is needed as data rates continue to increase, in PCIe 8.0: Enabling The Next Generation Of High Bandwidth Systems.
Quadric’s Steve Roddy provides a concrete example of how architectural boundaries influence system behavior, in Heterogeneous NPU Data Movement: What The Execution Flow Shows.
Synopsys’ Brett Mudock finds that first silicon alone is no longer sufficient for establishing next-generation designs, in Early HBM4 Validation Points The Way For Next-Generation AI And HPC Systems.
Expedera’s Sharad Chole contends that edge intelligence is hampered by underutilized compute and the solution is to think in terms of packets, not layers, in The Coming Breakup Between AI And The Cloud.
Siemens’ Sudarshan Deo digs into power delivery, now spanning stacked dies, interposers, bridges, and packages connected by thousands of micro-bumps and TSVs, in Power Integrity Without Blind Spots: A System Level Approach To 3D-ICs.
Arm’s Odin Shen outlines a complete pipeline that can run on a single workstation for training a humanoid robot to walk over rough terrain, in Rethinking Robotics Reinforcement Learning: A Practical Humanoid Training Workflow.
Cadence’s Tanushri Shah discusses validation of an optimized data movement architecture that ensures arithmetic units receive a steady stream of data every cycle, in Redefining AI Inference With New Silicon Architecture.
Sponsor White Papers
AI At The Edge Ubiquitous, Agentic, Multimodal, And Hardware-Accelerated
Limitations—such as latency, bandwidth costs, privacy concerns, catastrophic consequences in the event of failure, and dependency on continuous connectivity—are driving interest in Edge AI.
Engineer’s Guide To Simulating Electronics Cooling: eBook
How to use intelligent thermal simulation to predict and solve cooling issues early.
Inside The AI Accelerator: Essential IP Design Solutions: eBook
How next‑gen AI accelerators break past single‑chip limits using advanced IP, high‑speed interconnects, memory interfaces, and multi‑die architectures.
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