Top Stories
Taking Power Much More Seriously
Without the benefits of scaling to help reduce power consumption, design teams must take responsibility themselves. It all starts with the architecture.
Solving Thermal Coupling Issues In Complex Chips
Challenges mount, especially in 3D-ICs and chips developed at leading-edge nodes.
Balancing Power And Heat In Advanced Chip Designs
Both need to be dealt with at all stages of the design flow. Why it’s now everyone’s problem.
On-Chip Power Distribution Modeling Becomes Essential Below 7nm
Why and when it’s needed, and what tools and technologies are required.
Videos
Managing IP In Heterogeneous Designs
How an interoperability layer is essential to tracking IP.
Blogs
Ansys’ Kelly Damalou and Matt Commens explain why former PCB scale problems are now squeezed into a single stacked or interconnected device, in The Computational Electromagnetics Simulation Challenge Of 3D-IC.
Fraunhofer IIS EAS’ Jens Michael Warmuth points to two methods for preventing failures in critical systems, in Predictive Health Monitoring In Functional Safety.
Synopsys’ Ron Lowman traces how the dynamics are changing to prioritize energy use over per-unit chip costs, in Accelerating IoT Designs: Designing For Low Power In The Era Of Smart Everything.
Siemens’ Derong Yan looks at ways to define voltage and current limits within which an ESD protection device operates during an event, in Are You Paying Proper Attention To Your ESD Design Windows?
Rambus’ Frank Ferro finds that keeping inference processors fed with data requires extremely high bandwidth memory, in GDDR6 Memory Enables High-Performance AI/ML Inference.
Cadence’s Paul McLellan details how mobile is moving toward a convergence of connectivity, computing, control, and content, in EDPS: Transitioning From 5G To 6G.
Ansys’ Pete Gasperini explains how airports and aircraft could have been ready for the rollout of 5G, in An Update On 5G And Aircraft Safety.
Arm’s Paul Williamson reviews recent efforts to simplify IoT development for manufacturers and increase compatibility for consumers, in Developers Embrace Standards To Accelerate Growth Opportunities For The IoT.
Ansys’ Marc Swinnen pitches the IDEAS technical event (online only, Dec. 6th), which will feature Intel, Qualcomm, Nvidia, IBM, Samsung, and more discussing their chip design experience, in Challenges And Solutions In Chip Design.
Sponsor White Papers
Complete Reliability Verification For Multiple-Power-Domain Designs
How to detect and correct reliability issues in advanced chip layouts.
Enabling Accurate Electronic-Photonic Co-Design With A Synergetic Workflow On GlobalFoundries Fotonix Platform
A workflow that leverages the Ansys Lumerical, Cadence, and GlobalFoundries (GF) Fotonix process design kit for electronic-photonic co-design.
Innovate By Customized Instructions, But Without Fragmenting The Ecosystem
The design considerations for SoC designers when they deploy hardware accelerators, and how software developers access the accelerators.
Unleash The Potential Of CFD
A huge leap in computational fluid dynamics (CFD) technology by advancing numerical algorithms, SRS, and HPC using the same commercial code.
How Low Can You Go? Pushing The Limits Of Transistors
The enablement of embedded memories and logic libraries to achieve extreme low power.
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